This file provides all the configurations provided by ADC module of Freescale MPC563 power-pc MCU. More...
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Defines | |
#define | ADC_DISABLE_STOP_MODE 0 |
This macro defines the value for disabling the ADC stop mode. | |
#define | ADC_ENABLE_STOP_MODE 1 |
This macro defines the value for enabling the ADC stop mode. | |
#define | ADC_IGNORE_FREEZE 0 |
This macro defines the value for ignoring the freeze commands provided in CCWs. | |
#define | ADC_ENABLE_FREEZE 1 |
This macro defines the value for enabling the freeze commands provided in CCWs. | |
#define | ADC_MODE_LOCK_ENABLE 0 |
This macro defines the value for locking the ADC mode of operation. This prevents accidental change in mode of operation. | |
#define | ADC_MODE_LOCK_DISABLE 1 |
This macro defines the value for unlocking the ADC mode of operation. This will enable change in mode of operation. | |
#define | ADC_INT_PRIO(Q1Prio, Q2Prio) ((((U16)(Q2Prio)) << 5) | (Q1Prio)) |
This macro used to develop the QADCINT reg value by grouping all the different field values. | |
#define | ADC_Q1_COMP_INT_DISABLE 0 |
This macro used to disable completion interrupt for Queue-1. | |
#define | ADC_Q1_COMP_INT_ENABLE 1 |
This macro used to enable completion interrupt for Queue-1. | |
#define | ADC_Q1_PAUSE_INT_DISABLE 0 |
This macro used to disable pause interrupt for Queue-1. | |
#define | ADC_Q1_PAUSE_INT_ENABLE 1 |
This macro used to enable pause interrupt for Queue-1. | |
#define | ADC_Q2_COMP_INT_DISABLE 0 |
This macro used to disable completion interrupt for Queue-2. | |
#define | ADC_Q2_COMP_INT_ENABLE 1 |
This macro used to enable completion interrupt for Queue-2. | |
#define | ADC_Q2_PAUSE_INT_DISABLE 0 |
This macro used to disable pause interrupt for Queue-2. | |
#define | ADC_Q2_PAUSE_INT_ENABLE 1 |
This macro used to enable pause interrupt for Queue-2. | |
#define | ADC_TOT_CCW 64 |
This macro defines the total no.of CCWs available in each ADC converter module. | |
#define | QADC_MOD_A (( struct QADC64_tag *) (INTERNAL_MEMORY_BASE + 0x304800)) |
This defines the address for the ADC converter module A register group. | |
#define | QADC_MOD_B (( struct QADC64_tag *) (INTERNAL_MEMORY_BASE + 0x304C00)) |
This defines the address for the ADC converter module B register group. |
This file provides all the configurations provided by ADC module of Freescale MPC563 power-pc MCU.
Definition in file adc_Cfg.h.
#define ADC_TOT_CCW 64 |
#define QADC_MOD_A (( struct QADC64_tag *) (INTERNAL_MEMORY_BASE + 0x304800)) |
#define QADC_MOD_B (( struct QADC64_tag *) (INTERNAL_MEMORY_BASE + 0x304C00)) |