00001 /******************************************************************************/ 00002 /** \file adc.h 00003 * 00004 * \brief This file provides all the APIs provided by QADC64E module 00005 * of Freescale MPC563 power-pc MCU 00006 * 00007 * \version 1.0A - Initial Draft 00008 * \date 25 June 2010 00009 * 00010 * \version 1.1A - Design changed to support run-time CCW addition and 00011 * configuration 00012 * \date 16 July 2010 00013 ******************************************************************************/ 00014 #ifndef ADC_H 00015 #define ADC_H 00016 /****************************************************************************** 00017 Include Files 00018 ******************************************************************************/ 00019 #include "mpc563.h" 00020 00021 /****************************************************************************** 00022 Type defines 00023 ******************************************************************************/ 00024 /** \def QADC_PORT_A 00025 * \brief This defines the PORT-A mask */ 00026 #define QADC_PORT_A 0x0000 00027 /** \def QADC_PORT_B 00028 * \brief This defines the PORT-B mask */ 00029 #define QADC_PORT_B 0x0080 00030 00031 typedef enum 00032 { 00033 QADC_PORT_A0 = QADC_PORT_A, 00034 QADC_PORT_A1, 00035 QADC_PORT_A2, 00036 QADC_PORT_A3, 00037 QADC_PORT_A4, 00038 QADC_PORT_A5, 00039 QADC_PORT_A6, 00040 QADC_PORT_A7, 00041 QADC_PORT_B0 = QADC_PORT_B, 00042 QADC_PORT_B1, 00043 QADC_PORT_B2, 00044 QADC_PORT_B3, 00045 QADC_PORT_B4, 00046 QADC_PORT_B5, 00047 QADC_PORT_B6, 00048 QADC_PORT_B7, 00049 }QADC_Ports; 00050 00051 typedef enum 00052 { 00053 QADC_CONFIG_IN, 00054 QADC_CONFIG_OUT, 00055 }QADC_PortConfigType; 00056 00057 typedef enum 00058 { 00059 PORT_VAL_LOW, 00060 PORT_VAL_HIGH, 00061 }QADC_PortVal; 00062 00063 typedef enum 00064 { 00065 QADC_IO_FAIL, 00066 QADC_IO_SUCCESS, 00067 QADC_IO_INVALID_CFG_TYPE, 00068 QADC_IO_INVALID_MOD_ID, 00069 QADC_IO_INVALID_PORT_ID, 00070 00071 }QADC_IO_OpStatus; 00072 00073 /*************************************************************************** 00074 ************* QADCMCR - Module Configuration Register settings ************* 00075 ****************************************************************************/ 00076 /** \addtogroup QADCMCR_REG_SETTINGS QADCMCR register settings */ /*@{*/ 00077 00078 /* QADC mode of operation */ 00079 typedef enum 00080 { 00081 /** \brief ADC "Legacy Mode" of operation */ 00082 ADC_LEGACY_OP_MODE, 00083 /** \brief ADC "Enhanced Mode" of operation */ 00084 ADC_ENHANCED_OP_MODE 00085 }QADC_OpMode; 00086 00087 /* QADC register access permission */ 00088 typedef enum 00089 { 00090 /** Defines the value to configure the module configuration register, 00091 test register, and interrupt register as supervisor-only 00092 data space. Access to all other locations is unrestricted */ 00093 ADC_LIMITED_SUPV_ACC, 00094 /** Defines the value to configure all QADC64E registers and CCW/result 00095 tables as supervisor-only data space */ 00096 ADC_FULL_SUPV_ACC, 00097 }QADC_RegAcc; 00098 /*@}*/ 00099 00100 /*************************************************************************** 00101 ************************** QACR0 - Control Reg-0 *************************** 00102 ****************************************************************************/ 00103 /** \defgroup QACR0_REG_SETTINGS QACR0 register settings */ /*@{*/ 00104 00105 /** \brief This enum provides the External Multiplexed mode selection */ 00106 typedef enum 00107 { 00108 /** Select internal MUX configuration */ 00109 ADC_MUX_MODE_INT, 00110 /** Sselect external MUX configuration */ 00111 ADC_MUX_MODE_EXT, 00112 }QADC_ExtMuxSel; 00113 00114 /** \brief This enum provides the ADC External trigger assignment */ 00115 typedef enum 00116 { 00117 /** Selects external trigger signal ETRIG1 for queue-1 and external 00118 trigger signal ETRIG2 for queue-2 */ 00119 ADC_ETRIG1_Q1_ETRIG2_Q2, 00120 /** Select external trigger signal ETRIG1 for queue-2 and external 00121 trigger signal ETRIG2 for queue-1 */ 00122 ADC_ETRIG1_Q2_ETRIG2_Q1, 00123 }QADC_ExtTrig_Sel; 00124 00125 /*@}*/ 00126 /*************************************************************************** 00127 ****************************** QACR1 - Control Reg-1 *********************** 00128 ****************************************************************************/ 00129 /** \addtogroup QACR1_REG_SETTINGS QACR1 register settings */ /*@{*/ 00130 00131 /** \brief Provides Queue-1 Single scan operation status */ 00132 typedef enum 00133 { 00134 /** Disables single scan operation for Queue-1 */ 00135 ADC_Q1_SINGLE_SCAN_DISABLE, 00136 /** Enables single scan operation for Queue-1 */ 00137 ADC_Q1_SINGLE_SCAN_ENABLE, 00138 }QADC_Q1_SingleScanOpt; 00139 00140 /* Queue-1 Operating mode */ 00141 /** \brief This enum provides all Queue-1 operation modes */ 00142 typedef enum 00143 { 00144 /** \brief Disabled mode, conversions do not occur */ 00145 ADC_OP_Q1_DISABLE, 00146 /** \brief Software triggered single-scan mode (started with SSE1) */ 00147 ADC_OP_Q1_SW_TRIG_SINGLE_SCAN, 00148 /** \brief External trigger rising edge single-scan mode */ 00149 ADC_OP_Q1_EXT_TRIG_RISING_EDGE_SINGLE_SCAN, 00150 /** \brief External trigger falling edge single-scan mode */ 00151 ADC_OP_Q1_EXT_TRIG_FALLING_EDGE_SINGLE_SCAN, 00152 /** \brief Interval timer single-scan mode: time = QCLK period x (2^7) */ 00153 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_128_QCLK, 00154 /** \brief Interval timer single-scan mode: time = QCLK period x (2^8) */ 00155 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_256_QCLK, 00156 /** \brief Interval timer single-scan mode: time = QCLK period x (2^9) */ 00157 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_512_QCLK, 00158 /** \brief Interval timer single-scan mode: time = QCLK period x (2^10) */ 00159 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_1024_QCLK, 00160 /** \brief Interval timer single-scan mode: time = QCLK period x (2^11) */ 00161 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_2048_QCLK, 00162 /** \brief Interval timer single-scan mode: time = QCLK period x (2^12) */ 00163 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_4096_QCLK, 00164 /** \brief Interval timer single-scan mode: time = QCLK period x (2^13) */ 00165 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_8192_QCLK, 00166 /** \brief Interval timer single-scan mode: time = QCLK period x (2^14) */ 00167 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_16384_QCLK, 00168 /** \brief Interval timer single-scan mode: time = QCLK period x (2^15) */ 00169 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_32768_QCLK, 00170 /** \brief Interval timer single-scan mode: time = QCLK period x (2^16) */ 00171 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_65536_QCLK, 00172 /** \brief Interval timer single-scan mode: time = QCLK period x (2^17) */ 00173 ADC_OP_Q1_INTVAL_TIMER_SINGLE_SCAN_131072_QCLK, 00174 /** \brief External gated single-scan mode (started with SSE1) */ 00175 ADC_OP_Q1_EXT_GATED_SINGLE_SCAN, 00176 /** \brief Reserved mode */ 00177 ADC_OP_Q1_RESERVED_1, 00178 /** \brief Software triggered continuous-scan mode */ 00179 ADC_OP_Q1_SW_TRIG_CONTINOUS_SCAN, 00180 /** \brief External trigger rising edge continuous-scan mode */ 00181 ADC_OP_Q1_EXT_TRIG_RISING_EDGE_CONTINOUS_SCAN, 00182 /** \brief External trigger falling edge continuous-scan mode */ 00183 ADC_OP_Q1_EXT_TRIG_FALLING_EDGE_CONTINOUS_SCAN, 00184 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^7) */ 00185 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_128_QCLK, 00186 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^8) */ 00187 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_256_QCLK, 00188 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^9) */ 00189 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_512_QCLK, 00190 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^10) */ 00191 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_1024_QCLK, 00192 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^11) */ 00193 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_2048_QCLK, 00194 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^12) */ 00195 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_4096_QCLK, 00196 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^13) */ 00197 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_8192_QCLK, 00198 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^14) */ 00199 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_16384_QCLK, 00200 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^15) */ 00201 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_32768_QCLK, 00202 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^16) */ 00203 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_65536_QCLK, 00204 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^17) */ 00205 ADC_OP_Q1_PERIO_TIMER_CONT_SCAN_131072_QCLK, 00206 /** \brief External gated continuous-scan mode */ 00207 ADC_OP_Q1_EXT_GATED_CONTINOUS_SCAN, 00208 }ADC_Q1_OpModes; 00209 00210 /*@}*/ 00211 00212 /*************************************************************************** 00213 ******************************** QACR2 - Control Reg-2 ********************* 00214 ****************************************************************************/ 00215 /** \addtogroup QACR2_REG_SETTINGS QACR2 register settings */ /*@{*/ 00216 /** \brief Provides Queue-2 Single scan operation status */ 00217 typedef enum 00218 { 00219 /** Disables single scan operation for Queue-2 */ 00220 ADC_Q2_SINGLE_SCAN_DISABLE, 00221 /** Enables single scan operation for Queue-2 */ 00222 ADC_Q2_SINGLE_SCAN_ENABLE, 00223 }QADC_Q2_SingleScanOpt; 00224 00225 /* Queue-2 Operating mode */ 00226 /** \brief This enum provides all Queue-2 operation modes */ 00227 typedef enum 00228 { 00229 /** \brief Disabled mode, conversions do not occur */ 00230 ADC_OP_Q2_DISABLE, 00231 /** \brief Software triggered single-scan mode (started with SSE2) */ 00232 ADC_OP_Q2_SW_TRIG_SINGLE_SCAN, 00233 /** \brief External trigger rising edge single-scan mode */ 00234 ADC_OP_Q2_EXT_TRIG_RISING_EDGE_SINGLE_SCAN, 00235 /** \brief External trigger falling edge single-scan mode */ 00236 ADC_OP_Q2_EXT_TRIG_FALLING_EDGE_SINGLE_SCAN, 00237 /** \brief Interval timer single-scan mode: time = QCLK period x (2^7) */ 00238 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_128_QCLK, 00239 /** \brief Interval timer single-scan mode: time = QCLK period x (2^8) */ 00240 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_256_QCLK, 00241 /** \brief Interval timer single-scan mode: time = QCLK period x (2^9) */ 00242 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_512_QCLK, 00243 /** \brief Interval timer single-scan mode: time = QCLK period x (2^10) */ 00244 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_1024_QCLK, 00245 /** \brief Interval timer single-scan mode: time = QCLK period x (2^11) */ 00246 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_2048_QCLK, 00247 /** \brief Interval timer single-scan mode: time = QCLK period x (2^12) */ 00248 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_4096_QCLK, 00249 /** \brief Interval timer single-scan mode: time = QCLK period x (2^13) */ 00250 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_8192_QCLK, 00251 /** \brief Interval timer single-scan mode: time = QCLK period x (2^14) */ 00252 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_16384_QCLK, 00253 /** \brief Interval timer single-scan mode: time = QCLK period x (2^15) */ 00254 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_32768_QCLK, 00255 /** \brief Interval timer single-scan mode: time = QCLK period x (2^16) */ 00256 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_65536_QCLK, 00257 /** \brief Interval timer single-scan mode: time = QCLK period x (2^17) */ 00258 ADC_OP_Q2_INTVAL_TIMER_SINGLE_SCAN_131072_QCLK, 00259 /** \brief Reserved mode */ 00260 ADC_OP_Q2_RESERVED_1, 00261 /** \brief Reserved mode */ 00262 ADC_OP_Q2_RESERVED_2, 00263 /** \brief Software triggered continuous-scan mode */ 00264 ADC_OP_Q2_SW_TRIG_CONTINOUS_SCAN, 00265 /** \brief External trigger rising edge continuous-scan mode */ 00266 ADC_OP_Q2_EXT_TRIG_RISING_EDGE_CONTINOUS_SCAN, 00267 /** \brief External trigger falling edge continuous-scan mode */ 00268 ADC_OP_Q2_EXT_TRIG_FALLING_EDGE_CONTINOUS_SCAN, 00269 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^7) */ 00270 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_128_QCLK, 00271 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^8) */ 00272 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_256_QCLK, 00273 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^9) */ 00274 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_512_QCLK, 00275 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^10) */ 00276 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_1024_QCLK, 00277 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^11) */ 00278 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_2048_QCLK, 00279 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^12) */ 00280 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_4096_QCLK, 00281 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^13) */ 00282 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_8192_QCLK, 00283 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^14) */ 00284 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_16384_QCLK, 00285 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^15) */ 00286 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_32768_QCLK, 00287 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^16) */ 00288 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_65536_QCLK, 00289 /** \brief Periodic timer continuous-scan mode: time = QCLK period x (2^17) */ 00290 ADC_OP_Q2_PERIO_TIMER_CONT_SCAN_131072_QCLK, 00291 /** \brief External gated continuous-scan mode */ 00292 ADC_OP_Q2_EXT_GATED_CONTINOUS_SCAN, 00293 /** \brief Reserved mode */ 00294 ADC_OP_Q2_RESERVED_3, 00295 }ADC_Q2_OpModes; 00296 00297 /** \brief This enum defines the Queue-2 CCW Resume position */ 00298 typedef enum 00299 { 00300 /** Begin executing with the first CCW in queue 2 or the current 00301 sub-queue, After suspension */ 00302 ADC_Q2_RESUME_FROM_START_POS, 00303 /**Begin executing with the aborted CCW in queue 2, After suspension */ 00304 ADC_Q2_RESUME_FROM_SUSPENDED_POS, 00305 }QADC_Q2_ResumePos; 00306 00307 /*@}*/ 00308 /*************************************************************************** 00309 *************************** QASR0 - Status Register ************************ 00310 ****************************************************************************/ 00311 /** \defgroup QASR0_REG_SETTINGS QASR0 register settings */ /*@{*/ 00312 /* Queue (Q1 and Q2) status */ 00313 /** \brief This enum provides Queue-1 and Queue-2 operation status */ 00314 typedef enum 00315 { 00316 /** \brief queue 1 idle, queue 2 idle */ 00317 ADC_Q_IDLE, 00318 /** \brief queue 1 idle, queue 2 paused */ 00319 ADC_Q1_IDLE_Q2_PAUSED, 00320 /** \brief queue 1 idle, queue 2 active */ 00321 ADC_Q1_IDLE_Q2_ACTIVE, 00322 /** \brief queue 1 idle, queue 2 trigger pending */ 00323 ADC_Q1_IDLE_Q2_PENDING, 00324 /** \brief queue 1 paused, queue 2 idle */ 00325 ADC_Q1_PAUSED_Q2_IDLE, 00326 /** \brief queue 1 paused, queue 2 paused */ 00327 ADC_Q1_PAUSED_Q2_PAUSED, 00328 /** \brief queue 1 paused, queue 2 active */ 00329 ADC_Q1_PAUSED_Q2_ACTIVE, 00330 /** \brief queue 1 paused, queue 2 trigger pending */ 00331 ADC_Q1_PAUSED_Q2_PENDING, 00332 /** \brief queue 1 active, queue 2 idle */ 00333 ADC_Q1_ACTIVE_Q2_IDLE, 00334 /** \brief queue 1 active, queue 2 paused */ 00335 ADC_Q1_ACTIVE_Q2_PAUSED, 00336 /** \brief queue 1 active, queue 2 suspended */ 00337 ADC_Q1_ACTIVE_Q2_SUSPENDED, 00338 /** \brief queue 1 active, queue 2 trigger pending */ 00339 ADC_Q1_ACTIVE_Q2_PENDING, 00340 /** \brief Reserved_1 */ 00341 ADC_Q_STATUS_1, 00342 /** \brief Reserved_2 */ 00343 ADC_Q_STATUS_2, 00344 /** \brief Reserved_3 */ 00345 ADC_Q_STATUS_3, 00346 /** \brief Reserved_4 */ 00347 ADC_Q_STATUS_4 00348 }ADC_Q_Status; 00349 /*@}*/ 00350 00351 /*************************************************************************** 00352 ******************** CCW - Conversion Command Word Format ****************** 00353 ****************************************************************************/ 00354 /** \defgroup CCW_SETTINGS CCW settings */ /*@{*/ 00355 00356 /** \brief Enum provides pause status after each CCW execution */ 00357 typedef enum 00358 { 00359 /** Defines the value to disable pause after the current CCW execution */ 00360 ADC_PAUSE_DISABLE, 00361 /** Defines the value to enable pause after the current CCW execution */ 00362 ADC_PAUSE_ENABLE, 00363 }QADC_CCW_PauseVal; 00364 00365 /* Amplifier bypass selection in legacy mode of operation */ 00366 typedef enum 00367 { 00368 /** Disables the Sample amplifier bypass for the signal conversion */ 00369 ADC_AMPL_BYPASS_DISABLE, 00370 /** Enables the Sample amplifier bypass for a conversion, and 00371 subsequently changes the timing */ 00372 ADC_AMPL_BYPASS_ENABLE, 00373 }QADC_CCW_AmplBypassVal; 00374 00375 /* High reference selection for enhanced mode of operation */ 00376 typedef enum 00377 { 00378 /** VRH is used as high reference */ 00379 ADC_REF_VRH, 00380 /** AltRef signal is used as the high reference */ 00381 ADC_REF_ALTREF, 00382 }QADC_CCW_RefVal; 00383 00384 00385 /* Input sample time */ 00386 /** \brief This enum provides possible sampling times for a conversion 00387 00388 for Legacy mode of operation: select clocks of 2x, 4x, 8x, 16x 00389 for Enhanced mode of operation: select clocks of 2x, 8x 00390 */ 00391 typedef enum 00392 { 00393 /** \brief Sample time is 2x times QADC clock */ 00394 ADC_SAMPL_TIME_2_QCLK, 00395 /** \brief Sample time is 4x times QADC clock */ 00396 ADC_SAMPL_TIME_4_QCLK, 00397 /** \brief Sample time is 8x times QADC clock */ 00398 ADC_SAMPL_TIME_8_QCLK, 00399 /** \brief Sample time is 16x times QADC clock */ 00400 ADC_SAMPL_TIME_16_QCLK 00401 }ADC_InputSampleTime; 00402 00403 /*@}*/ 00404 00405 00406 /** \typedef QADC_ResultFormat 00407 * \brief This typedefine enum provides the ADC conversion result read 00408 format */ 00409 typedef enum 00410 { 00411 /** \brief Read the result in right justified unsigned format */ 00412 ADC_RIGHT_JUST_UNSIGN, 00413 /** \brief Read the result in left justified signed format */ 00414 ADC_LEFT_JUST_SIGN, 00415 /** \brief Read the result in left justified unsigned format */ 00416 ADC_LEFT_JUST_UNSIGN 00417 }QADC_ResultFormat; 00418 00419 /** \typedef QADC_Module_ID 00420 * \brief This typedefine enum provides the ADC conversion modules */ 00421 typedef enum 00422 { 00423 /** \brief This is channel-A ADC converter */ 00424 ADC_MOD_A, 00425 /** \brief This is channel-B ADC converter */ 00426 ADC_MOD_B, 00427 /** \brief Defines the total no of ADC converters supported */ 00428 ADC_TOT_MOD 00429 }QADC_Module_ID; 00430 00431 /** \typedef QADC_Drv_Status 00432 * \brief This enum typedefine provides various status of ADC driver 00433 module */ 00434 typedef enum 00435 { 00436 /** This indicates that driver is not initialized */ 00437 ADC_DRV_UNINIT, 00438 /** This indicates that driver is initialized but not ready for conversion */ 00439 ADC_DRV_INIT, 00440 /** Unknown ADC converter state */ 00441 ADC_UNKNOWN_STATE, 00442 }QADC_Drv_Status; 00443 00444 /** \typedef QADC_DrvOpStatus 00445 * \brief This enum typedefine provides various operation states 00446 if the ADC driver */ 00447 typedef enum 00448 { 00449 /** Driver operation failed due to unknwon reason */ 00450 ADC_OP_FAIL, 00451 /** Driver operation success */ 00452 ADC_OP_SUCCESS, 00453 /** Driver operation failed due to invalid ADC converter module ID */ 00454 ADC_OP_INVALID_MOD_ID, 00455 /** Driver operation failed due to invalid CCW ID */ 00456 ADC_OP_INVALID_CCW_ID, 00457 /** Driver operation failed due to invalid user provided data */ 00458 ADC_OP_INVALID_DATA, 00459 /** Driver operation failed as the current state of driver does not support the requested action */ 00460 ADC_OP_UNSUPP_STATE, 00461 /** Read operation failed, as the read format provided is not supported */ 00462 ADC_OP_UNSUPP_RD_FMT, 00463 }QADC_DrvOpStatus;; 00464 00465 /** \typedef QADC_ConvMod_CCWs 00466 * \brief This enum typedefine provides all the CCW IDs 00467 registered for both ADC converter module A and B */ 00468 typedef enum 00469 { 00470 /* ADC converter module CCWs */ 00471 ADC_MOD_CCW_0, 00472 ADC_MOD_CCW_1, 00473 ADC_MOD_CCW_2, 00474 ADC_MOD_CCW_3, 00475 ADC_MOD_CCW_4, 00476 ADC_MOD_CCW_5, 00477 ADC_MOD_CCW_6, 00478 ADC_MOD_CCW_7, 00479 ADC_MOD_CCW_8, 00480 ADC_MOD_CCW_9, 00481 ADC_MOD_CCW_10, 00482 ADC_MOD_CCW_11, 00483 ADC_MOD_CCW_12, 00484 ADC_MOD_CCW_13, 00485 ADC_MOD_CCW_14, 00486 ADC_MOD_CCW_15, 00487 ADC_MOD_CCW_16, 00488 ADC_MOD_CCW_17, 00489 ADC_MOD_CCW_18, 00490 ADC_MOD_CCW_19, 00491 ADC_MOD_CCW_20, 00492 ADC_MOD_CCW_21, 00493 ADC_MOD_CCW_22, 00494 ADC_MOD_CCW_23, 00495 ADC_MOD_CCW_24, 00496 ADC_MOD_CCW_25, 00497 ADC_MOD_CCW_26, 00498 ADC_MOD_CCW_27, 00499 ADC_MOD_CCW_28, 00500 ADC_MOD_CCW_29, 00501 ADC_MOD_CCW_30, 00502 ADC_MOD_CCW_31, 00503 ADC_MOD_CCW_32, 00504 ADC_MOD_CCW_33, 00505 ADC_MOD_CCW_34, 00506 ADC_MOD_CCW_35, 00507 ADC_MOD_CCW_36, 00508 ADC_MOD_CCW_37, 00509 ADC_MOD_CCW_38, 00510 ADC_MOD_CCW_39, 00511 ADC_MOD_CCW_40, 00512 ADC_MOD_CCW_41, 00513 ADC_MOD_CCW_42, 00514 ADC_MOD_CCW_43, 00515 ADC_MOD_CCW_44, 00516 ADC_MOD_CCW_45, 00517 ADC_MOD_CCW_46, 00518 ADC_MOD_CCW_47, 00519 ADC_MOD_CCW_48, 00520 ADC_MOD_CCW_49, 00521 ADC_MOD_CCW_50, 00522 ADC_MOD_CCW_51, 00523 ADC_MOD_CCW_52, 00524 ADC_MOD_CCW_53, 00525 ADC_MOD_CCW_54, 00526 ADC_MOD_CCW_55, 00527 ADC_MOD_CCW_56, 00528 ADC_MOD_CCW_57, 00529 ADC_MOD_CCW_58, 00530 ADC_MOD_CCW_59, 00531 ADC_MOD_CCW_60, 00532 ADC_MOD_CCW_61, 00533 ADC_MOD_CCW_62, 00534 ADC_MOD_CCW_63, 00535 ADC_MOD_CCW_TOT, 00536 }QADC_ConvMod_CCWs; 00537 00538 /* Structure used to hold all configuration of each ADC module converter */ 00539 /** \brief This structure holds all conversion configuration of any ADC 00540 converter module */ 00541 typedef struct 00542 { 00543 /** ADC converter module ID */ 00544 QADC_Module_ID ModID; 00545 /** ADC converter operational mode */ 00546 QADC_OpMode OpMode; 00547 /** ADC converter register access */ 00548 QADC_RegAcc RegAcc; 00549 /** ADC converter external Mux selection */ 00550 QADC_ExtMuxSel ExtMux; 00551 /** External triggering type*/ 00552 QADC_ExtTrig_Sel ExtTrigType; 00553 /** Single scan enable/ disable */ 00554 QADC_Q1_SingleScanOpt Q1_SingleScan; 00555 /** Queue-1 operation mode */ 00556 ADC_Q1_OpModes Q1_OpMode; 00557 /** Queue-2 single scan enable/ disable */ 00558 QADC_Q2_SingleScanOpt Q2_SingleScan; 00559 /** Queue-2 operation mode */ 00560 ADC_Q2_OpModes Q2_OpMode; 00561 /** Queue-2 resume position*/ 00562 QADC_Q2_ResumePos Q2_ResumeType; 00563 /** ADC converter Queue-1 priority */ 00564 U8 u8Q1IntPrio; 00565 /** ADC converter Queue-2 priority */ 00566 U8 u8Q2IntPrio; 00567 /** Presclar clock high time for ADC conversion */ 00568 U8 u8PresclClkHighTime; 00569 /** Presclar clock low time for ADC conversion */ 00570 U8 u8PresclClkLowTime; 00571 /** Queue-2 CCW begin position in the total queue */ 00572 U8 u8Q2Begin; 00573 }QADC_ConvModConf; 00574 00575 /** \brief Application callback function prototype to call after 00576 ADC conversion complete */ 00577 typedef void (*ConvComplCB)(QADC_ConvMod_CCWs CCW_ID, U16 u16Data); 00578 00579 /** \brief This enum provides mask settings for calling application 00580 call-back functions. */ 00581 typedef enum 00582 { 00583 /** This will disable to call the application registered call-back 00584 function afetr ADC conversion completes */ 00585 ADC_CB_NONE = 0x0000, 00586 /** This mask will work if you have enabled Pause settings for this 00587 CCW. As the queue execution will enter into pause state after 00588 execution of the CCW, the MCU will call the registered 00589 call-back function for this CCW */ 00590 ADC_CB_PAUSE_MSK = 0x8000, 00591 /** This mask will enable to call the application registered 00592 call-back function for this CCW, after the whole ADC CCW 00593 queue execution will complete */ 00594 ADC_CB_COMPL_MSK = 0x4000, 00595 /** This mask will enable to call the application registered 00596 call-back function after the pause and queue completion */ 00597 ADC_CB_PAUSE_COMPL_MASK = 0xC000, 00598 }ADC_ApplCBMasks; 00599 00600 /** \brief This enum holds different interrupt status supported */ 00601 typedef enum 00602 { 00603 /** QADC Queue-1 completion interrupt status */ 00604 ADC_Q1_COMPL_STATUS, 00605 /** QADC Queue-1 pause interrupt status */ 00606 ADC_Q1_PAUSE_STATUS, 00607 /** QADC Queue-2 completion interrupt status */ 00608 ADC_Q2_COMPL_STATUS, 00609 /** QADC Queue-2 pause interrupt status */ 00610 ADC_Q2_PAUSE_STATUS, 00611 /** QADC Queue-1 overrun interrupt status */ 00612 ADC_Q1_TRIG_OVERRUN, 00613 /** QADC Queue-2 overrun interrupt status */ 00614 ADC_Q2_TRIG_OVERRUN, 00615 }ADC_INT_Type; 00616 00617 00618 /** \brief This structure defines the data for each CCW and the 00619 Application call-back function for that conversion */ 00620 typedef struct 00621 { 00622 /** Call-back function to be called after this CCW conversion is complete */ 00623 ConvComplCB ApplCB; 00624 /** This defines the ADC converter module ID */ 00625 QADC_Module_ID ModID; 00626 /** Defines the CCW ID (CCW location), where the CCW will be stored */ 00627 QADC_ConvMod_CCWs CCW_ID; 00628 /** If Pause value is provided, the queue execution will be 00629 suspended and will be resumed after getting a new trigger 00630 signal. If the CCW is in Queue-1, the execution will 00631 resume from the next CCW. If this CCW is in Queue-2, 00632 the resume position will be depend on the resume position 00633 defined in the ADC converter module configuration */ 00634 QADC_CCW_PauseVal PauseVal; 00635 /** Amplifier bypass selection for the analog channel in 00636 legacy mode of operation. FO renhanced mode of oepration, 00637 this value is not used */ 00638 QADC_CCW_AmplBypassVal BypassVal; 00639 /** This is used for reference selection in enhanced mode of operation */ 00640 QADC_CCW_RefVal RefVal; 00641 /** ADC conversion time for this CCW */ 00642 ADC_InputSampleTime SampTime; 00643 /** Callback mask setting. Use masks values from the enum 00644 "ADC_ApplCBMasks" */ 00645 ADC_ApplCBMasks ApplCB_Mask; 00646 /** Analog input channel No. \n 00647 - 0 to 3, 48 to 59 => (If Ext MUX is not selected) 00648 - 0 to 31, 48 to 51, 55 to 59 => (If Ext MUX is selected) 00649 - 4 to 31 (if Ext MUX is not selected), 32 to 47 => The low 00650 reference level (VRL) is converted 00651 - 60 to 62 => Sample amplifier will not be used. The value 00652 of VRL, VRH, or (VRH – VRL)/2 is placed 00653 directly into the converter 00654 - 63 => End of queue 00655 */ 00656 U8 u8ChannelNo; 00657 }QADC_CCW_ApplData; 00658 00659 00660 /** \brief This structure defines the data for reading the result of 00661 any ADC conversion */ 00662 typedef struct 00663 { 00664 /** ADc converter module ID */ 00665 QADC_Module_ID ModID; 00666 /** ADC converter CCW ID (queue Index) */ 00667 QADC_ConvMod_CCWs QueueID; 00668 /** Result read format requested */ 00669 QADC_ResultFormat ReadFormat; 00670 /** Buffer to get theresult value from the ADC driver */ 00671 U16 u16Data; 00672 }QADC_CCW_ApplResultData; 00673 00674 00675 00676 /****************************************************************************** 00677 API Prototypes 00678 ******************************************************************************/ 00679 QADC_DrvOpStatus ADC_Init(QADC_ConvModConf* ModConf); 00680 QADC_DrvOpStatus ADC_AddCCW(QADC_CCW_ApplData* CCW_Conf); 00681 QADC_DrvOpStatus ADC_Read (QADC_CCW_ApplResultData* ResultData); 00682 void ADC_ConvStop(QADC_Module_ID ModID); 00683 void ADC_Off(QADC_Module_ID ModID); 00684 00685 /* Interrupt status */ 00686 Bool ADC_InterruptStatus(QADC_Module_ID ModID, ADC_INT_Type IntType); 00687 void ADC_ClearInterrupt(QADC_Module_ID ModID, ADC_INT_Type IntType); 00688 00689 QADC_IO_OpStatus QADC_PortConfig(QADC_Module_ID ModID, QADC_Ports PortID, QADC_PortConfigType Type); 00690 QADC_IO_OpStatus QADC_PortSet(QADC_Module_ID ModID, QADC_Ports PortID, QADC_PortVal Value); 00691 QADC_IO_OpStatus QADC_PortGet(QADC_Module_ID ModID, QADC_Ports PortID, QADC_PortVal* Value); 00692 #endif