| Stepper_Qsys | Stepper_Qsys
1.0 |
| 2011.12.07.09:49:39 | Generation Report |
| Output Directory | D:/uni/Altera/VHDL/SOC2011_Qsys/ | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Files | D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/Stepper_Qsys.v (637892 bytes VERILOG)
D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu.ocp (864 bytes OTHER) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu.sdc (4410 bytes SDC) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu.v (307896 bytes VERILOG_ENCRYPT) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu_ic_tag_ram.mif (504 bytes MIF) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu_jtag_debug_module_sysclk.v (7286 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu_jtag_debug_module_tck.v (8704 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu_jtag_debug_module_wrapper.v (10757 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu_mult_cell.v (6360 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu_ociram_default_contents.mif (5714 bytes MIF) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu_oci_test_bench.v (1545 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu_rf_ram_a.mif (600 bytes MIF) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu_rf_ram_b.mif (600 bytes MIF) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_steppercpu_test_bench.v (29734 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_sysid_qsys.v (1463 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_jtag_uart.v (24243 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_jtag_uart_input_mutex.dat (3 bytes OTHER) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_jtag_uart_input_stream.dat (10 bytes OTHER) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_jtag_uart_output_stream.dat (0 bytes OTHER) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_DE2_SRAM.v (28323 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_tristate_controller_translator.sv (7099 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_merlin_slave_translator.sv (16043 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_tristate_controller_aggregator.sv (9385 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_SRAM_Pin_Share.v (4426 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_SRAM_Pin_Share_pin_sharer.sv (3992 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_merlin_std_arbitrator_core.sv (8940 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_SRAM_Pin_Share_arbiter.sv (2852 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_SRAM_Conduit.sv (5028 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_hex0.v (2254 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_Switch.v (1951 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_UpDownKey.v (1978 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_RunStopKey.v (3571 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_IF.vhd (5375 bytes VHDL) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_DE2_lcd.v (2355 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_merlin_master_translator.sv (16802 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_merlin_slave_agent.sv (19132 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10373 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_avalon_sc_fifo.v (32228 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_merlin_master_agent.sv (8686 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_addr_router.sv (6478 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_addr_router_001.sv (10778 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_id_router.sv (6055 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_id_router_001.sv (6067 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_id_router_002.sv (5985 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_merlin_traffic_limiter.sv (12802 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_merlin_burst_adapter.sv (37064 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_reset_controller.v (3595 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_cmd_xbar_demux.sv (4129 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_cmd_xbar_demux_001.sv (13739 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_merlin_arbitrator.sv (9460 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_cmd_xbar_mux.sv (10436 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_rsp_xbar_demux.sv (4121 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_rsp_xbar_demux_002.sv (3495 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_rsp_xbar_mux.sv (11249 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_rsp_xbar_mux_001.sv (23546 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/altera_merlin_width_adapter.sv (35861 bytes SYSTEM_VERILOG) D:/uni/Altera/VHDL/SOC2011_Qsys/Stepper_Qsys/synthesis/submodules/Stepper_Qsys_irq_mapper.sv (1914 bytes SYSTEM_VERILOG) |
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| Instantiations |
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