Test Project
counter
behv
Signals
|
Processes
behv Architecture Reference
Processes
PROCESS_0
(
clock
,
count
,
clear
)
Counter logic.
Signals
count_reg
std_logic_vector
(
n
-
1
downto
0
)
The documentation for this class was generated from the following file:
vhdl/counter.vhd
Generated on Thu Jun 22 2017 13:33:17 for Test Project by
1.8.13