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ExampleComponent_BEH Architecture Reference

Entity Description: Here...
Register Definitions: Here...
IRQ Definitions: Here...
Block Diagram: Here...
More...

Functions

boolean   dump_xml ( [ impure ]

Processes

reg_ctrl_prc  ( dataClk )
 Capture RegisterBank control.
reg_stat_prc  ( dataClk )
 Write back register status.
reg_clr_prc  ( dataClk )
do_prc  ( dataClk )

Use Clauses

ctype_h 
strings_h 
stdio_h 

Constants

DATA_IN_WIDTH  natural := DATA_IN_INFO .BITS_PER_SYMBOL * DATA_IN_INFO .SYMBOLS_PER_BEAT
 
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DATA_OUT_WIDTH  natural := DATA_OUT_INFO .BITS_PER_SYMBOL * DATA_OUT_INFO .SYMBOLS_PER_BEAT
 Avalon-ST data out width.
REG_DATA_WIDTH  natural := 8
 Captures the default register bit width for registers not that dont have specifically defined bits.
CONTROL_REGISTER  RegisterLocation := init ( " example_control " , REG_COMPONENT_START_ADDR + toInt ( x " 00 " ) , 3 , RW_REG_CFG )
A_CTRL_BIT  RegisterBit := 0
STATUS_REGISTER  RegisterLocation := init ( " exmaple_status " , REG_COMPONENT_START_ADDR + toInt ( x " 01 " ) , 8 , RO_STATUS_REG_CFG )
ALMOST_FULL_BIT  RegisterBit := FIFO_WR_ALMOST_FULL_BIT
FULL_BIT  RegisterBit := FIFO_WR_FULL_BIT
ALMOST_EMPTY_BIT  RegisterBit := FIFO_RD_ALMOST_EMPTY_BIT
EMPTY_BIT  RegisterBit := FIFO_RD_EMPTY_BIT
COUNT_CONFIG_REGISTER  RegisterLocation := init ( " count_config " , REG_COMPONENT_START_ADDR + toInt ( x " 02 " ) , 2 , RW_WR_CLEAR_REG_CFG )
LOAD_BIT  RegisterBit := 0
PAUSE_BIT  RegisterBit := 1
COUNT_INIT_REGISTER  RegisterLocation := init ( " count_init " , REG_COMPONENT_START_ADDR + toInt ( x " 03 " ) , REG_DATA_WIDTH , RW_REG_CFG )
COUNT_STEP_REGISTER  RegisterLocation := init ( " count_step " , REG_COMPONENT_START_ADDR + toInt ( x " 04 " ) , REG_DATA_WIDTH , RW_REG_CFG )
FLAGS_REGISTER  RegisterLocation := init ( " flags " , REG_COMPONENT_START_ADDR + toInt ( x " 05 " ) , REG_DATA_WIDTH , RO_STATUS_RD_FLAG_REG_CFG )
IRQ_BIT  RegisterBit := 0
NUM_IRQ_BITS  natural := IRQ_BIT + 1
TRIGGER_IRQ_REGISTER  RegisterLocation := init ( " trigger_irq " , REG_COMPONENT_START_ADDR + toInt ( x " 06 " ) , NUM_IRQ_BITS , RW_REG_CFG )
LEVEL_IRQ_STATUS_REGISTER  RegisterLocation := init ( " level_irq_status " , toInt ( x " 08 " ) , NUM_IRQ_BITS , LEVEL_IRQ_REG_CFG )
LEVEL_IRQ_MASK_REGISTER  RegisterLocation := init ( " level_irq_mask " , toInt ( x " 09 " ) , NUM_IRQ_BITS , STD_IRQ_MASK_REG_CFG )
FALLING_EDGE_IRQ_STATUS_REGISTER  RegisterLocation := init ( " falling_edge_irq_status " , toInt ( x " 0A " ) , NUM_IRQ_BITS , FALLING_EDGE_IRQ_REG_CFG )
COMPONENT_REG_LOCATIONS  RegisterLocationArray := ( CONTROL_REGISTER , STATUS_REGISTER , COUNT_CONFIG_REGISTER , COUNT_INIT_REGISTER , COUNT_STEP_REGISTER , FLAGS_REGISTER , TRIGGER_IRQ_REGISTER , LEVEL_IRQ_STATUS_REGISTER , LEVEL_IRQ_MASK_REGISTER , FALLING_EDGE_IRQ_STATUS_REGISTER )
 All of the custom register locations.
VERSION  natural := 3
 Version number of this component.
STD_REG_LOC_CFG  StandardRegisterLocationsConfig := init ( ID_EXAMPLE_COMPONENT , VERSION , RISING_EDGE_IRQ , NUM_IRQ_BITS )
 Definition of this component's registers.
REGISTER_BANK_INFO  RegisterBankInfo := init ( STD_REG_LOC_CFG , COMPONENT_REG_LOCATIONS )
FIFO_DEPTH  natural := 8
 Depth used for both the input and output FIFO components.
FIFO_IN_FIFO_INFO  FIFOInfo := ( FIFO_TYPE = > RAM_SINGLE_RATE_FIFO , DEPTH = > FIFO_DEPTH , WR_ALMOST_FULL_CNT = > FIFO_DEPTH - 1 , WR_ALMOST_EMPTY_CNT = > FIFO_REMOVE_COUNT , RD_ALMOST_FULL_CNT = > FIFO_REMOVE_COUNT , RD_ALMOST_EMPTY_CNT = > 1 , SHOW_AHEAD = > true )
 Used to configure the input FIFO.
FIFO_OUT_FIFO_INFO  FIFOInfo := init ( RAM_SINGLE_RATE_FIFO , FIFO_DEPTH )
 Used to configure the output FIFO.
DUMP_XML_FILES  boolean := dump_xml

Subtypes

DATA_IN_RANGE  natural range ( DATA_IN_WIDTH - 1 ) downto 0
 Avalon-ST data in width.
DATA_OUT_RANGE  natural range ( DATA_OUT_WIDTH - 1 ) downto 0
REG_DATA_RANGE  natural range ( REG_DATA_WIDTH - 1 ) downto 0
SOME_CTRL_RANGE  natural range 2 downto 1

Signals

reset_in  std_logic
data_reset  std_logic
control_bit  std_logic
control_field  std_logic_vector ( SOME_CTRL_RANGE )
load  std_logic
pause  std_logic
count_init  std_logic_vector ( REG_DATA_RANGE )
count_step  std_logic_vector ( REG_DATA_RANGE )
clear_flags  std_logic
flags  std_logic_vector ( REG_DATA_RANGE )
irq_flag  std_logic
reg_ctrl  RegisterControlIntf
reg_status  RegisterStatusIntf
fifo_in_status  AvalonMMSlaveToFabricIntf
fifo_in_data_out  AvalonSTSourceToSinkIntf
fifo_in_data_out_rsp  AvalonSTSinkToSourceIntf
fifo_out_data_in  AvalonSTSourceToSinkIntf
fifo_out_data_in_rsp  AvalonSTSinkToSourceIntf

Instantiations

register_bank_map  registerbank
soft_reset_map  softreset
fifo_in_map  fifo
fifo_out_map  fifo

Detailed Description

Entity Description: Here...
Register Definitions: Here...
IRQ Definitions: Here...
Block Diagram: Here...

Definition at line 265 of file ExampleComponent.vhd.

Member Function Documentation

boolean dump_xml ( ) impure
Function

Definition at line 531 of file ExampleComponent.vhd.

reg_ctrl_prc (   dataClk )
get

Capture RegisterBank control.

Definition at line 648 of file ExampleComponent.vhd.

reg_stat_prc (   dataClk  
)
Process

Write back register status.

Definition at line 719 of file ExampleComponent.vhd.

reg_clr_prc (   dataClk  
)
Process

Definition at line 755 of file ExampleComponent.vhd.

do_prc (   dataClk )
get

Definition at line 847 of file ExampleComponent.vhd.

Member Data Documentation

DATA_IN_WIDTH natural := DATA_IN_INFO .BITS_PER_SYMBOL * DATA_IN_INFO .SYMBOLS_PER_BEAT
Constant


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Definition at line 280 of file ExampleComponent.vhd.

DATA_IN_RANGE natural range ( DATA_IN_WIDTH - 1 ) downto 0
Subtype

Avalon-ST data in width.

Definition at line 281 of file ExampleComponent.vhd.

DATA_OUT_WIDTH natural := DATA_OUT_INFO .BITS_PER_SYMBOL * DATA_OUT_INFO .SYMBOLS_PER_BEAT
Constant

Avalon-ST data out width.

Definition at line 284 of file ExampleComponent.vhd.

DATA_OUT_RANGE natural range ( DATA_OUT_WIDTH - 1 ) downto 0
Subtype

Definition at line 285 of file ExampleComponent.vhd.

REG_DATA_WIDTH natural := 8
Constant

Captures the default register bit width for registers not that dont have specifically defined bits.

Definition at line 292 of file ExampleComponent.vhd.

REG_DATA_RANGE natural range ( REG_DATA_WIDTH - 1 ) downto 0
Subtype

Definition at line 293 of file ExampleComponent.vhd.

CONTROL_REGISTER RegisterLocation := init ( " example_control " , REG_COMPONENT_START_ADDR + toInt ( x " 00 " ) , 3 , RW_REG_CFG )
Constant

Definition at line 318 of file ExampleComponent.vhd.

A_CTRL_BIT RegisterBit := 0
Constant

Custom single bit in the control register.

Definition at line 320 of file ExampleComponent.vhd.

SOME_CTRL_RANGE natural range 2 downto 1
Subtype

This range defines a field within the register and can be used for access.

Definition at line 323 of file ExampleComponent.vhd.

All of the custom register locations.

Definition at line 429 of file ExampleComponent.vhd.

VERSION natural := 3
Constant

Version number of this component.

Definition at line 451 of file ExampleComponent.vhd.

STD_REG_LOC_CFG StandardRegisterLocationsConfig := init ( ID_EXAMPLE_COMPONENT , VERSION , RISING_EDGE_IRQ , NUM_IRQ_BITS )
Constant

Definition of this component's registers.

There are multiple types of RegisterBank supported. Standard and small. A STANDARD_?_REG_BANK is used when a component is in stand alone mode and the memory interface needs access to the register values. SMALL_REG_BANK is used when the register bank is in a sub-component and we only need minor status which will be tied to a parent register bank for communication over the memory interface.

Definition at line 460 of file ExampleComponent.vhd.

REGISTER_BANK_INFO RegisterBankInfo := init ( STD_REG_LOC_CFG , COMPONENT_REG_LOCATIONS )
Constant

Definition at line 462 of file ExampleComponent.vhd.

FIFO_DEPTH natural := 8
Constant

Depth used for both the input and output FIFO components.

Definition at line 469 of file ExampleComponent.vhd.

FIFO_IN_FIFO_INFO FIFOInfo := ( FIFO_TYPE = > RAM_SINGLE_RATE_FIFO , DEPTH = > FIFO_DEPTH , WR_ALMOST_FULL_CNT = > FIFO_DEPTH - 1 , WR_ALMOST_EMPTY_CNT = > FIFO_REMOVE_COUNT , RD_ALMOST_FULL_CNT = > FIFO_REMOVE_COUNT , RD_ALMOST_EMPTY_CNT = > 1 , SHOW_AHEAD = > true )
Constant

Used to configure the input FIFO.

Definition at line 472 of file ExampleComponent.vhd.

FIFO_OUT_FIFO_INFO FIFOInfo := init ( RAM_SINGLE_RATE_FIFO , FIFO_DEPTH )
Constant

Used to configure the output FIFO.

Definition at line 481 of file ExampleComponent.vhd.

reset_in std_logic
Signal

Definition at line 488 of file ExampleComponent.vhd.

data_reset std_logic
Signal

Definition at line 489 of file ExampleComponent.vhd.

control_bit std_logic
Signal

Definition at line 492 of file ExampleComponent.vhd.

control_field std_logic_vector ( SOME_CTRL_RANGE )
Signal

Definition at line 493 of file ExampleComponent.vhd.

load std_logic
Signal

Definition at line 496 of file ExampleComponent.vhd.

pause std_logic
Signal

Definition at line 497 of file ExampleComponent.vhd.

count_init std_logic_vector ( REG_DATA_RANGE )
Signal

Definition at line 499 of file ExampleComponent.vhd.

count_step std_logic_vector ( REG_DATA_RANGE )
Signal

Definition at line 500 of file ExampleComponent.vhd.

clear_flags std_logic
Signal

Definition at line 503 of file ExampleComponent.vhd.

flags std_logic_vector ( REG_DATA_RANGE )
Signal

Definition at line 504 of file ExampleComponent.vhd.

irq_flag std_logic
Signal

Definition at line 507 of file ExampleComponent.vhd.

reg_ctrl RegisterControlIntf
Signal

Definition at line 510 of file ExampleComponent.vhd.

reg_status RegisterStatusIntf
Signal

Definition at line 511 of file ExampleComponent.vhd.

fifo_in_status AvalonMMSlaveToFabricIntf
Signal

Definition at line 514 of file ExampleComponent.vhd.

fifo_in_data_out AvalonSTSourceToSinkIntf
Signal

Definition at line 515 of file ExampleComponent.vhd.

fifo_in_data_out_rsp AvalonSTSinkToSourceIntf
Signal

Definition at line 516 of file ExampleComponent.vhd.

fifo_out_data_in AvalonSTSourceToSinkIntf
Signal

Definition at line 519 of file ExampleComponent.vhd.

fifo_out_data_in_rsp AvalonSTSinkToSourceIntf
Signal

Definition at line 520 of file ExampleComponent.vhd.

ctype_h
Package

Definition at line 527 of file ExampleComponent.vhd.

strings_h
Package

Definition at line 528 of file ExampleComponent.vhd.

stdio_h
Package

Definition at line 529 of file ExampleComponent.vhd.

DUMP_XML_FILES boolean := dump_xml
Constant

Definition at line 553 of file ExampleComponent.vhd.

register_bank_map registerbank
Instantiation

Definition at line 591 of file ExampleComponent.vhd.

soft_reset_map softreset
Instantiation

Definition at line 623 of file ExampleComponent.vhd.

fifo_in_map fifo
Instantiation

Definition at line 804 of file ExampleComponent.vhd.

fifo_out_map fifo
Instantiation

Definition at line 911 of file ExampleComponent.vhd.


The documentation for this class was generated from the following files: