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ExampleSubSystem.vhd
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1 -- ************************************************************************** --
2 -- ************* BittWare Incorporated ************* --
3 -- ************* 9 Hills Ave, Concord, NH 03301 ************* --
4 -- ************************************************************************** --
5 -- LEGAL NOTICE: --
6 -- Copyright (c) 2011 BittWare, Inc. --
7 -- The user is hereby granted a non-exclusive license to use and or --
8 -- modify this code provided that it runs on BittWare hardware. --
9 -- Usage of this code on non-BittWare hardware without the express --
10 -- written permission of BittWare is strictly prohibited. --
11 -- --
12 -- E-mail: support@bittware.com Tel: 603-226-0404 --
13 -- ************************************************************************** --
14 -- ABSTRACT:
15 -- ************************************************************************** --
16 -- DESIGN NOTES:
17 -- ************************************************************************** --
18 
19 library ieee;
20 use ieee.std_logic_1164.all;
21 use ieee.numeric_std.all;
22 
23 library work;
24 use work.UtilityPkg.all;
25 use work.BoardInfoPkg.all;
26 use work.AvalonPkg.all;
27 use work.ExamplePkg.all;
28 use work.DMAPkg.all;
29 use work.MemoryMappedPkg.all;
30 use work.SubSystemPkg.all;
31 
32 --------------------------------------------------------------------------------
33 -- ABSTRACT:
34 --------------------------------------------------------------------------------
41 
42 --------------------------------------------------------------------------------
43 -- DESIGN DETAILS:
44 --------------------------------------------------------------------------------
48 
49 --------------------------------------------------------------------------------
50 -- NOTES:
51 --------------------------------------------------------------------------------
53 
54 --------------------------------------------------------------------------------
55 -- TODO:
56 --------------------------------------------------------------------------------
58 
59 --------------------------------------------------------------------------------
60 -- BUGS
61 --------------------------------------------------------------------------------
63 
64 --------------------------------------------------------------------------------
65 -- RETURN LINKS:
66 --------------------------------------------------------------------------------
68 
69 --------------------------------------------------------------------------------
71 --------------------------------------------------------------------------------
72 generic (
74  BOARD_INFO : BoardInfo;
76  SLAVE_OUT_INFO : AvalonMMSlaveInfo;
78  DATA_IN_INFO : AvalonSTInfoArray;
80  DATA_OUT_INFO : AvalonSTInfoArray;
83 );
84 port(
87  slaveInClk : in std_logic;
88  slaveInReset : in std_logic;
89  slaveInIRQ : out AvalonIRQSenderIntf;
90  slaveIn : in AvalonMMFabricToSlaveIntf;
91  slaveInRsp : out AvalonMMSlaveToFabricIntf;
95  slaveOutClk : in std_logic;
96  slaveOutReset : in std_logic;
97  slaveOut : out AvalonMMFabricToSlaveIntf;
98  slaveOutRsp : in AvalonMMSlaveToFabricIntf;
102  dataClk : in std_logic;
103  dataReset : in std_logic;
107  dataIn : in AvalonSTSourceToSinkIntfArray;
108  dataInRsp : out AvalonSTSinkToSourceIntfArray;
112  dataOut : out AvalonSTSourceToSinkIntfArray;
113  dataOutRsp : in AvalonSTSinkToSourceIntfArray
115 );
116 
117 --------------------------------------------------------------------------------
118 end entity;
119 --------------------------------------------------------------------------------
120 
121 --------------------------------------------------------------------------------
122 -- BRIEF LINKS:
123 --------------------------------------------------------------------------------
129 
130 --------------------------------------------------------------------------------
131 -- BLOCK DIAGRAM:
132 --------------------------------------------------------------------------------
135 
136 --------------------------------------------------------------------------------
137 -- RETURN LINKS:
138 --------------------------------------------------------------------------------
140 
141 --------------------------------------------------------------------------------
142 architecture ExampleSubSystem_BEH of ExampleSubSystem is
143 --------------------------------------------------------------------------------
144 
145  --------------------------------------------
146  -- Aliasing
147  --------------------------------------------
148 
149  alias data_in : AvalonSTSourceToSinkIntfArray(0 to dataIn'length-1) is dataIn;
150  alias data_in_rsp : AvalonSTSinkToSourceIntfArray(0 to dataInRsp'length-1) is dataInRsp;
151 
152  alias data_out : AvalonSTSourceToSinkIntfArray(0 to dataOut'length-1) is dataOut;
153  alias data_out_rsp : AvalonSTSinkToSourceIntfArray(0 to dataOutRsp'length-1) is dataOutRsp;
154 
155  --------------------------------------------
156  -- Constants
157  --------------------------------------------
158 
159  constant SLAVE_IN_INFO : AvalonMMSlaveInfoArray := toArray( init(16, 32) );
160 
161  constant STREAMING_TO_SLAVE_SUB_SYSTEM_INFO : StreamingToSlaveSubSystemInfo := ( INTERNAL_DMA_READERS => EXAMPLE_SUB_SYSTEM_INFO.NUM_DMA_ENGINES,
162  INTERNAL_DMA_WRITERS => EXAMPLE_SUB_SYSTEM_INFO.NUM_DMA_ENGINES,
163  DIRECT_DMA_READERS => 0,
164  DIRECT_DMA_WRITERS => 0,
165  DMA_CONTROLLER_INFO => init(1024, 128, BOTH),
166  SLAVE_WINDOW_INFO => init(init(false, 1, 0)) );
167 
168  --------------------------------------------
169  -- Signals
170  --------------------------------------------
171 
172  signal data_in_clk : std_logic_vector(0 to dataIn'length-1);
173  signal data_in_reset : std_logic_vector(0 to dataIn'length-1);
174  signal data_out_clk : std_logic_vector(0 to dataOut'length-1);
175  signal data_out_reset : std_logic_vector(0 to dataOut'length-1);
176 
177  ---------------------------
178  -- Dump XML
179  ---------------------------
180 
181  -- synthesis translate_off
182  use work.ctype_h.all;
183  use work.strings_h.all;
184  use work.stdio_h.all;
185 
186  impure function dump_xml return boolean is
187  constant NAME : string := ExampleSubSystem'path_name;
188  constant FILE_NAME : FileName := init( "project_config.xml" );
189  variable xml_file : CFILE;
190  begin
191  xml_file := fopen(FILE_NAME, "a");
192 
193  if( xml_file = 0 ) then
194  report "ERROR: ExampleSubSystem.vhd - Cannot Open XML File " & FILE_NAME
195  severity failure;
196  end if;
197 
198  fprintf(xml_file, "<ComponentInfo type=%s name=%s>\n", addQuotes("ExampleSubSystem"), addQuotes(NAME) );
199  fprintf(xml_file, "%s", getXML("slave_out_info", SLAVE_OUT_INFO));
200  for ii in DATA_IN_INFO'range loop
201  fprintf(xml_file, "%s", getXML("data_in_info", ii, DATA_IN_INFO(ii)));
202  end loop;
203  for ii in DATA_OUT_INFO'range loop
204  fprintf(xml_file, "%s", getXML("data_out_info", ii, DATA_OUT_INFO(ii)));
205  end loop;
206  fprintf(xml_file, "%s", getXML("example_sub_system_info.num_dma_engines", EXAMPLE_SUB_SYSTEM_INFO.NUM_DMA_ENGINES));
207  fprintf(xml_file, "</ComponentInfo>\n");
208 
209  fclose(xml_file);
210 
211  return true;
212  end function;
213 
214  constant DUMP_XML_FILES : boolean := dump_xml;
215  -- synthesis translate_on
216 
217 --------------------------------------------------------------------------------
218 begin
219 --------------------------------------------------------------------------------
220 
221  data_in_clk <= (others => dataClk);
222  data_in_reset <= (others => dataReset);
223  data_out_clk <= (others => dataClk);
224  data_out_reset <= (others => dataReset);
225 
226  streaming_to_slave_sub_system_map : StreamingToSlaveSubSystem
227  generic map (
228  BOARD_INFO => BOARD_INFO,
229  SLAVE_IN_INFO => SLAVE_IN_INFO ,
230  SLAVE_OUT_INFO => SLAVE_OUT_INFO,
231  DATA_IN_INFO => DATA_IN_INFO ,
232  DATA_OUT_INFO => DATA_OUT_INFO ,
233  STREAMING_TO_SLAVE_SUB_SYSTEM_INFO => STREAMING_TO_SLAVE_SUB_SYSTEM_INFO
234  )
235  port map (
236  slaveInClk(0) => slaveInClk,
237  slaveInReset(0) => slaveInReset ,
238  slaveInIRQ => slaveInIRQ,
239  slaveIn(0) => slaveIn,
240  slaveInRsp(0) => slaveInRsp,
241  slaveOutClk => slaveOutClk,
242  slaveOutReset => slaveOutReset ,
243  slaveOut => slaveOut ,
244  slaveOutRsp => slaveOutRsp,
245  dataInClk => data_in_clk ,
246  dataInReset => data_in_reset ,
247  dataIn => data_in,
248  dataInRsp => data_in_rsp,
249  dataOutClk => data_out_clk ,
250  dataOutReset => data_out_reset,
251  dataOut => data_out ,
252  dataOutRsp => data_out_rsp
253  );
254 
255 --------------------------------------------------------------------------------
256 end architecture;
257 --------------------------------------------------------------------------------