Example
Bugreport
|
Entities | |
Behavioral | architecture |
Libraries | |
ieee |
Use Clauses | |
ieee.std_logic_1164.all | |
ieee.numeric_std.all | |
IEEE.math_real.all |
Generics | |
RATIO | Integer range 6 to 100 := 6 |
Ports | |
ACLK | in std_logic |
ARESETn | in std_logic |
s_axi_AWVALID | in std_logic |
s_axi_AWREADY | out std_logic |
s_axi_AWADDR | in std_logic_vector ( 3 downto 0 ) |
s_axi_WVALID | in std_logic |
s_axi_WREADY | out std_logic |
s_axi_WDATA | in std_logic_vector ( 31 downto 0 ) |
s_axi_WSTRB | in std_logic_vector ( 3 downto 0 ) |
s_axi_BVALID | out std_logic |
s_axi_BREADY | in std_logic |
s_axi_ARVALID | in std_logic |
s_axi_ARREADY | out std_logic |
s_axi_ARADDR | in std_logic_vector ( 3 downto 0 ) |
s_axi_RVALID | out std_logic |
s_axi_RREADY | in std_logic |
s_axi_RDATA | out std_logic_vector ( 31 downto 0 ) |
s_axis_TVALID | in std_logic |
s_axis_TREADY | out std_logic |
s_axis_TDATA | in std_logic_vector ( 23 downto 0 ) |
s_axis_TSTRB | in std_logic_vector ( 2 downto 0 ) |
s_axis_TLAST | in std_logic |
m_axis_TVALID | out std_logic |
m_axis_TREADY | in std_logic |
m_axis_TDATA | out std_logic_vector ( 15 downto 0 ) |
m_axis_TSTRB | out std_logic_vector ( 1 downto 0 ) |
m_axis_TLAST | out std_logic |