00001 ///////////////////////////////////////////////////////////////////// 00002 //// //// 00003 //// Mini-RISC-1 //// 00004 //// Prescaler and Wachdog Counter //// 00005 //// //// 00006 //// //// 00007 //// Author: Rudolf Usselmann //// 00008 //// rudi@asics.ws //// 00009 //// //// 00010 //// //// 00011 //// D/L from: http://www.opencores.org/cores/minirisc/ //// 00012 //// //// 00013 ///////////////////////////////////////////////////////////////////// 00014 //// //// 00015 //// Copyright (C) 2000-2002 Rudolf Usselmann //// 00016 //// www.asics.ws //// 00017 //// rudi@asics.ws //// 00018 //// //// 00019 //// This source file may be used and distributed without //// 00020 //// restriction provided that this copyright statement is not //// 00021 //// removed from the file and that any derivative work contains //// 00022 //// the original copyright notice and the associated disclaimer.//// 00023 //// //// 00024 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// 00025 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// 00026 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// 00027 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// 00028 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 00029 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// 00030 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// 00031 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// 00032 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// 00033 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 00034 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// 00035 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// 00036 //// POSSIBILITY OF SUCH DAMAGE. //// 00037 //// //// 00038 ///////////////////////////////////////////////////////////////////// 00039 00040 // CVS Log 00041 // 00042 // $Id: presclr_wdt.v,v 1.2 2002/09/27 15:35:40 rudi Exp $ 00043 // 00044 // $Date: 2002/09/27 15:35:40 $ 00045 // $Revision: 1.2 $ 00046 // $Author: rudi $ 00047 // $Locker: $ 00048 // $State: Exp $ 00049 // 00050 // Change History: 00051 // $Log: presclr_wdt.v,v $ 00052 // Revision 1.2 2002/09/27 15:35:40 rudi 00053 // Minor update to newer devices ... 00054 // 00055 // 00056 // 00057 // 00058 // 00059 // 00060 // 00061 // 00062 // 00063 // 00064 // 00065 00066 00067 `timescale 1ns / 10ps 00068 00069 // Prescaler and Wachdog Counter 00070 module presclr_wdt(clk, rst, tcki, option, tmr0_we, tmr0_cnt_en, wdt_en, wdt_clr, wdt_to); 00071 input clk; 00072 input rst; 00073 input tcki; 00074 input [5:0] option; 00075 input tmr0_we; 00076 output tmr0_cnt_en; 00077 input wdt_en, wdt_clr; 00078 output wdt_to; 00079 00080 00081 reg [7:0] prescaler; 00082 reg [7:0] wdt; 00083 reg tmr0_cnt_en; 00084 reg tcki_r; 00085 reg wdt_to; 00086 wire tose; 00087 wire tosc; 00088 wire psa; 00089 wire [2:0] ps; 00090 wire tcki_a, tcki_b; 00091 wire presclr_ce; 00092 wire prsclr_clr; 00093 wire wdt_to_direct; 00094 reg presclr_out, presclr_out_r1; 00095 reg presclr_out_next; 00096 wire [7:0] presclr_plus_1, wdt_plus_1; 00097 wire [7:0] prescaler_next, prescaler_next1; 00098 wire [7:0] wdt_next, wdt_next1; 00099 00100 // Inputs select 00101 assign ps = option[2:0]; 00102 assign psa = option[3]; 00103 assign tose = option[4]; 00104 assign tosc = option[5]; 00105 00106 always @(posedge clk) 00107 tcki_r <= #1 tcki; 00108 00109 assign tcki_a = tose ^ tcki_r; 00110 assign tcki_b = tosc ? tcki_a : 1'b1; 00111 assign presclr_ce = psa ? wdt_to_direct : tcki_b; 00112 00113 always @(posedge clk) 00114 tmr0_cnt_en <= #1 psa ? tcki_b : presclr_out; 00115 00116 // Prescaler 00117 assign prsclr_clr = psa ? wdt_clr : tmr0_we; 00118 00119 always @(posedge clk) 00120 if(rst | prsclr_clr) prescaler <= #1 8'h00; 00121 else 00122 if(presclr_ce) prescaler <= #1 prescaler + 8'h01; 00123 00124 always @(ps or prescaler) 00125 case(ps) 00126 3'd0: presclr_out_next = prescaler[0]; 00127 3'd1: presclr_out_next = prescaler[1]; 00128 3'd2: presclr_out_next = prescaler[2]; 00129 3'd3: presclr_out_next = prescaler[3]; 00130 3'd4: presclr_out_next = prescaler[4]; 00131 3'd5: presclr_out_next = prescaler[5]; 00132 3'd6: presclr_out_next = prescaler[6]; 00133 3'd7: presclr_out_next = prescaler[7]; 00134 endcase 00135 00136 always @(posedge clk) 00137 presclr_out_r1 <= #1 presclr_out_next; 00138 00139 always @(posedge clk) // Edge detector for prescaler output 00140 presclr_out <= #1 presclr_out_next & ~presclr_out_r1 & ~prsclr_clr; 00141 00142 // Wachdog timer 00143 always @(posedge clk) 00144 wdt_to <= #1 psa ? presclr_out : wdt_to_direct; 00145 00146 always @(posedge clk) 00147 if(rst | wdt_clr) wdt <= #1 8'h00; 00148 else 00149 if(wdt_en) wdt <= #1 wdt + 8'h01; // wdt_plus_1; 00150 00151 assign wdt_to_direct = (wdt == 8'hff); 00152 00153 endmodule