Processes | |
PROCESS_0 | ( clk ) |
Signals | |
irq_mask | std_logic_vector ( 3 downto 0 ) |
irq_unmasked | std_logic_vector ( 3 downto 0 ) |
irq_status | std_logic_vector ( 3 downto 0 ) |
reset_cnt | integer RANGE 0 TO 7 |
irq_read | std_logic |
wr | std_logic |
rd | std_logic |
w_err | std_logic |
Components | |
irq_w_error | |
irq_bl | Entity <irq_bl> |
PROCESS_0 | ( | clk ) |
irq_w_error [Component] |
irq_bl [Component] |
irq_mask std_logic_vector ( 3 downto 0 ) [Signal] |
irq_unmasked std_logic_vector ( 3 downto 0 ) [Signal] |
irq_status std_logic_vector ( 3 downto 0 ) [Signal] |
reset_cnt integer RANGE 0 TO 7 [Signal] |
irq_read std_logic [Signal] |
wr std_logic [Signal] |
rd std_logic [Signal] |
w_err std_logic [Signal] |
irq0 PORT [Port Map] |
irq1 PORT [Port Map] |
irq2 PORT [Port Map] |
irq3 PORT [Port Map] |
irq4 PORT [Port Map] |