prototype Entity Reference

Inheritance diagram for prototype:

prototype.structural

List of all members.


Libraries

ieee 

Packages

std_logic_1164 

Ports

clk  in std_logic
reset_n  in std_logic
ext_oe_n  out std_logic
ext_sram_we_n  out std_logic
proto5_sel_n  out std_logic
ext_flash_we_n  out std_logic
ext_be_n  out std_logic_vector ( 3 downto 0 )
ext_sram_addr17  out std_logic
ext_addr  out std_logic_vector ( 19 downto 0 )
ext_ram_select_0_n  out std_logic
ext_ram_select_1_n  out std_logic
ext_flash_select_n  out std_logic
ext_data  inout std_logic_vector ( 31 downto 0 )
uart_rxd  in std_logic
uart_txd  out std_logic
lcd  inout std_logic_vector ( 10 downto 0 )
leds  out std_logic_vector ( 1 downto 0 )
buttons  in std_logic_vector ( 11 downto 0 )
seven_seg  out std_logic_vector ( 15 downto 0 )
hdlc_rx  in std_logic
hdlc_tx  out std_ulogic
hdlc_rx1  in std_logic
hdlc_tx1  out std_ulogic
debug  out std_logic_vector ( 1 to 11 )
debug1  out std_logic_vector ( 1 to 11 )
kbd_y  out std_ulogic_vector ( 1 to 8 )
kbd_x  in std_logic_vector ( 1 to 10 )

Architectures

structural Architecture


Member Data Documentation

clk in [Port]

reset_n in [Port]

ext_oe_n out [Port]

ext_sram_we_n out [Port]

proto5_sel_n out [Port]

ext_flash_we_n out [Port]

ext_be_n out [Port]

ext_sram_addr17 out [Port]

ext_addr out [Port]

ext_ram_select_0_n out [Port]

ext_ram_select_1_n out [Port]

ext_flash_select_n out [Port]

ext_data inout [Port]

uart_rxd in [Port]

uart_txd out [Port]

lcd inout [Port]

leds out [Port]

buttons in [Port]

seven_seg out [Port]

hdlc_rx in [Port]

hdlc_tx out [Port]

hdlc_rx1 in [Port]

hdlc_tx1 out [Port]

debug out [Port]

debug1 out [Port]

kbd_y out [Port]

kbd_x in [Port]

ieee library [Library]

std_logic_1164 package [Package]


The documentation for this class was generated from the following file:

Generated on Sat Apr 19 14:13:51 2008 by  doxygen 1.5.4-20071103