tx_buffer.mixed Architecture Reference

Inheritance diagram for tx_buffer.mixed:

tx_buffer

List of all members.


Processes

PROCESS_10  ( clk )

Signals

rdadr  std_logic_vector ( 7 downto 0 )
wradr  std_logic_vector ( 7 downto 0 )
dav  std_logic
toggle  std_logic
dp_end  integer range 0 to 127
dp_adr  integer range 0 to 127

Components

frame_buffer 


Member Function Documentation

[Process]
PROCESS_10 ( clk )


Member Data Documentation

frame_buffer [Component]

rdadr std_logic_vector ( 7 downto 0 ) [Signal]

wradr std_logic_vector ( 7 downto 0 ) [Signal]

dav std_logic [Signal]

toggle std_logic [Signal]

dp_end integer range 0 to 127 [Signal]

dp_adr integer range 0 to 127 [Signal]

fb PORT [Port Map]


The documentation for this class was generated from the following file:

Generated on Sat Apr 19 14:13:56 2008 by  doxygen 1.5.4-20071103