Main Page
Design Units
Files
Design Unit List
Design Unit Hierarchy
Design Unit Members
prototype Member List
This is the complete list of members for
prototype
, including all inherited members.
address_to_the_hdlc1
prototype.structural
[Signal]
address_to_the_hdlc2
prototype.structural
[Signal]
buttons
prototype
[Port]
byteenablen_to_the_hdlc1
prototype.structural
[Signal]
byteenablen_to_the_hdlc2
prototype.structural
[Signal]
clk
prototype
[Port]
cnt
prototype.structural
[Signal]
debug
prototype
[Port]
debug1
prototype
[Port]
ext_addr
prototype
[Port]
ext_be_n
prototype
[Port]
ext_data
prototype
[Port]
ext_flash_select_n
prototype
[Port]
ext_flash_we_n
prototype
[Port]
ext_oe_n
prototype
[Port]
ext_ram_select_0_n
prototype
[Port]
ext_ram_select_1_n
prototype
[Port]
ext_sram_addr17
prototype
[Port]
ext_sram_we_n
prototype
[Port]
hdlc1
prototype.structural
[Class]
hdlc2
prototype.structural
[Class]
hdlc_interface
prototype.structural
[Component]
hdlc_rx
prototype
[Port]
hdlc_rx1
prototype
[Port]
hdlc_tx
prototype
[Port]
hdlc_tx1
prototype
[Port]
ieee
prototype
[Library]
in_port_to_the_keyboard_pio
prototype.structural
[Signal]
irq_from_the_hdlc1
prototype.structural
[Signal]
irq_from_the_hdlc2
prototype.structural
[Signal]
kbd
prototype.structural
[Class]
kbd_clk_en
prototype.structural
[Signal]
kbd_x
prototype
[Port]
kbd_y
prototype
[Port]
keyboard_decoder
prototype.structural
[Component]
lcd
prototype
[Port]
led1
prototype.structural
[Signal]
led2
prototype.structural
[Signal]
led3
prototype.structural
[Signal]
led4
prototype.structural
[Signal]
leds
prototype
[Port]
nios
prototype.structural
[Component]
nios0
prototype.structural
[Class]
off_chip_addr
prototype.structural
[Signal]
PROCESS_2
(clk)
prototype.structural
[Process]
proto5_sel_n
prototype
[Port]
readdata_from_the_hdlc1
prototype.structural
[Signal]
readdata_from_the_hdlc2
prototype.structural
[Signal]
readn_to_the_hdlc1
prototype.structural
[Signal]
readn_to_the_hdlc2
prototype.structural
[Signal]
reset
prototype.structural
[Signal]
reset_n
prototype
[Port]
select_to_the_hdlc1
prototype.structural
[Signal]
select_to_the_hdlc2
prototype.structural
[Signal]
seven_seg
prototype
[Port]
std_logic_1164
prototype
[Package]
uart_rxd
prototype
[Port]
uart_txd
prototype
[Port]
writedata_to_the_hdlc1
prototype.structural
[Signal]
writedata_to_the_hdlc2
prototype.structural
[Signal]
writen_to_the_hdlc1
prototype.structural
[Signal]
writen_to_the_hdlc2
prototype.structural
[Signal]
Generated on Sat Apr 19 14:13:51 2008 by
1.5.4-20071103