convergence Entity Reference

Inheritance diagram for convergence:

convergence.mixed

List of all members.


Libraries

ieee 

Packages

std_logic_1164 

Ports

clk  in std_logic
address_to_the_hdlc  in std_logic_vector ( 7 downto 0 )
cpu_be_n_to_the_hdlc  in std_logic
cpu_read_n_to_the_hdlc  in std_logic
cpu_write_n_to_the_hdlc  in std_logic
data_from_cpu_to_the_hdlc  in std_logic_vector ( 7 downto 0 )
data_to_cpu_from_the_hdlc  out std_logic_vector ( 7 downto 0 )
irq_from_the_hdlc  out std_logic
select_to_the_hdlc  in std_logic
rx_db  in std_logic_vector ( 7 downto 0 )
rx_db_adr  out std_logic_vector ( 6 downto 0 )
rx_db_len  in std_logic_vector ( 7 downto 0 )
rx_db_av  in std_logic
rx_db_ecrc  in std_logic
rx_db_eover  in std_logic
rx_db_read  out std_logic
tx_db  out std_logic_vector ( 7 downto 0 )
tx_db_adr  out std_logic_vector ( 6 downto 0 )
tx_db_en  out std_logic
tx_db_len  out std_logic_vector ( 6 downto 0 )
tx_db_start  out std_logic
tx_db_ready  in std_logic
clock_divisor  inout std_logic_vector ( 15 downto 0 )
loopback  inout std_logic
tx_crcfail  inout std_logic
rx_link  in std_logic
tx_link  inout std_logic
reset_in  in std_logic
wire_error  in std_logic
reset_out  inout std_logic

Architectures

mixed Architecture


Member Data Documentation

clk in [Port]

address_to_the_hdlc in [Port]

cpu_be_n_to_the_hdlc in [Port]

cpu_read_n_to_the_hdlc in [Port]

cpu_write_n_to_the_hdlc in [Port]

data_from_cpu_to_the_hdlc in [Port]

data_to_cpu_from_the_hdlc out [Port]

irq_from_the_hdlc out [Port]

select_to_the_hdlc in [Port]

rx_db in [Port]

rx_db_adr out [Port]

rx_db_len in [Port]

rx_db_av in [Port]

rx_db_ecrc in [Port]

rx_db_eover in [Port]

rx_db_read out [Port]

tx_db out [Port]

tx_db_adr out [Port]

tx_db_en out [Port]

tx_db_len out [Port]

tx_db_start out [Port]

tx_db_ready in [Port]

clock_divisor inout [Port]

loopback inout [Port]

tx_crcfail inout [Port]

rx_link in [Port]

tx_link inout [Port]

reset_in in [Port]

wire_error in [Port]

reset_out inout [Port]

ieee library [Library]

std_logic_1164 package [Package]


The documentation for this class was generated from the following file:

Generated on Sat Apr 19 14:13:49 2008 by  doxygen 1.5.4-20071103