clk | register_file | [Ports] |
rst | register_file | [Ports] |
rf_rd_bnk | register_file | [Ports] |
rf_rd_addr | register_file | [Ports] |
rf_rd_data | register_file | [Ports] |
rf_we | register_file | [Ports] |
rf_wr_bnk | register_file | [Ports] |
rf_wr_addr | register_file | [Ports] |
rf_wr_data | register_file | [Ports] |
clk | register_file | [Inputs] |
rst | register_file | [Inputs] |
rf_rd_bnk | register_file | [Inputs] |
rf_rd_addr | register_file | [Inputs] |
rf_rd_data | register_file | [Outputs] |
rf_we | register_file | [Inputs] |
rf_wr_bnk | register_file | [Inputs] |
rf_wr_addr | register_file | [Inputs] |
rf_wr_data | register_file | [Inputs] |
wr_data_tmp | register_file | [Registers] |
rd_wr_addr_equal | register_file | [Registers] |
ALWAYS_12clk | register_file | [Processes] |
ALWAYS_13clk | register_file | [Processes] |
rf0 | register_file | [Components] |