00001 ///////////////////////////////////////////////////////////////////// 00002 //// //// 00003 //// Mini-RISC-1 //// 00004 //// Prescaler and Wachdog Counter //// 00005 //// //// 00006 //// //// 00007 //// Author: Rudolf Usselmann //// 00008 //// rudi@asics.ws //// 00009 //// //// 00010 //// //// 00011 //// D/L from: http://www.opencores.org/cores/minirisc/ //// 00012 //// //// 00013 ///////////////////////////////////////////////////////////////////// 00014 //// //// 00015 //// Copyright (C) 2000-2002 Rudolf Usselmann //// 00016 //// www.asics.ws //// 00017 //// rudi@asics.ws //// 00018 //// //// 00019 //// This source file may be used and distributed without //// 00020 //// restriction provided that this copyright statement is not //// 00021 //// removed from the file and that any derivative work contains //// 00022 //// the original copyright notice and the associated disclaimer.//// 00023 //// //// 00024 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// 00025 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// 00026 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// 00027 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// 00028 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 00029 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// 00030 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// 00031 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// 00032 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// 00033 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 00034 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// 00035 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// 00036 //// POSSIBILITY OF SUCH DAMAGE. //// 00037 //// //// 00038 ///////////////////////////////////////////////////////////////////// 00039 00040 // CVS Log 00041 // 00042 // $Id: primitives_xilinx.v,v 1.3 2002/10/01 12:44:24 rudi Exp $ 00043 // 00044 // $Date: 2002/10/01 12:44:24 $ 00045 // $Revision: 1.3 $ 00046 // $Author: rudi $ 00047 // $Locker: $ 00048 // $State: Exp $ 00049 // 00050 // Change History: 00051 // $Log: primitives_xilinx.v,v $ 00052 // Revision 1.3 2002/10/01 12:44:24 rudi 00053 // Tweaked code a bit - trying to get it run faster ... 00054 // 00055 // Revision 1.2 2002/09/27 15:35:40 rudi 00056 // Minor update to newer devices ... 00057 // 00058 // 00059 // 00060 // 00061 // 00062 // 00063 // 00064 // 00065 // 00066 // 00067 // 00068 00069 `timescale 1ns / 10ps 00070 00071 // LIB_TAG 00072 // synopsys translate_off 00073 `include "XilinxCoreLib/C_ADDSUB_V1_0.v" 00074 `include "XilinxCoreLib/C_MUX_BUS_V1_0.v" 00075 `include "XilinxCoreLib/C_COMPARE_V1_0.v" 00076 `include "XilinxCoreLib/C_MUX_BIT_V1_0.v" 00077 `include "XilinxCoreLib/C_MEM_DP_BLOCK_V1_0.v" 00078 `include "XilinxCoreLib/C_REG_FD_V1_0.v" 00079 // synopsys translate_on 00080 // LIB_TAG_END 00081 00082 00083 // Mux 4:1 8 bits wide 00084 module mux4_8(sel, in0, in1, in2, in3, out); 00085 input [1:0] sel; 00086 input [7:0] in0, in1, in2, in3; 00087 output [7:0] out; 00088 00089 // INST_TAG 00090 xilinx_mux4_8 u0 ( 00091 .MA0(in0[0]), 00092 .MA1(in0[1]), 00093 .MA2(in0[2]), 00094 .MA3(in0[3]), 00095 .MA4(in0[4]), 00096 .MA5(in0[5]), 00097 .MA6(in0[6]), 00098 .MA7(in0[7]), 00099 00100 .MB0(in1[0]), 00101 .MB1(in1[1]), 00102 .MB2(in1[2]), 00103 .MB3(in1[3]), 00104 .MB4(in1[4]), 00105 .MB5(in1[5]), 00106 .MB6(in1[6]), 00107 .MB7(in1[7]), 00108 00109 .MC0(in2[0]), 00110 .MC1(in2[1]), 00111 .MC2(in2[2]), 00112 .MC3(in2[3]), 00113 .MC4(in2[4]), 00114 .MC5(in2[5]), 00115 .MC6(in2[6]), 00116 .MC7(in2[7]), 00117 00118 .MD0(in3[0]), 00119 .MD1(in3[1]), 00120 .MD2(in3[2]), 00121 .MD3(in3[3]), 00122 .MD4(in3[4]), 00123 .MD5(in3[5]), 00124 .MD6(in3[6]), 00125 .MD7(in3[7]), 00126 00127 .S0(sel[0]), 00128 .S1(sel[1]), 00129 00130 .O0(out[0]), 00131 .O1(out[1]), 00132 .O2(out[2]), 00133 .O3(out[3]), 00134 .O4(out[4]), 00135 .O5(out[5]), 00136 .O6(out[6]), 00137 .O7(out[7]) ); 00138 // INST_TAG_END 00139 00140 endmodule 00141 00142 /* 00143 // MOD_TAG 00144 module xilinx_mux4_8 (MA,MB,MC,MD,S,O); // synthesis black_box 00145 input [7:0] MA; 00146 input [7:0] MB; 00147 input [7:0] MC; 00148 input [7:0] MD; 00149 input [1:0] S; 00150 output [7:0] O; 00151 00152 // synopsys translate_off 00153 // synthesis translate_off 00154 C_MUX_BUS_V1_0 #( 00155 "00000000", 00156 1, 00157 0, 00158 0, 00159 0, 00160 0, 00161 0, 00162 1, 00163 0, 00164 0, 00165 0, 00166 0, 00167 4, 00168 0, 00169 2, 00170 "00000000", 00171 0, 00172 1, 00173 8) 00174 inst ( 00175 .MA(MA), 00176 .MB(MB), 00177 .MC(MC), 00178 .MD(MD), 00179 .S(S), 00180 .O(O)); 00181 // synthesis translate_on 00182 // synopsys translate_on 00183 endmodule 00184 // MOD_TAG_END 00185 * 00186 00187 // 8 bit comparator 00188 module cmp8_eq(a,b,eq); 00189 input [7:0] a,b; 00190 output eq; 00191 00192 // INST_TAG 00193 xilinx_cmp8_eq u0 ( 00194 .A0(a[0]), 00195 .A1(a[1]), 00196 .A2(a[2]), 00197 .A3(a[3]), 00198 .A4(a[4]), 00199 .A5(a[5]), 00200 .A6(a[6]), 00201 .A7(a[7]), 00202 00203 .B0(b[0]), 00204 .B1(b[1]), 00205 .B2(b[2]), 00206 .B3(b[3]), 00207 .B4(b[4]), 00208 .B5(b[5]), 00209 .B6(b[6]), 00210 .B7(b[7]), 00211 00212 .A_EQ_B(eq) ); 00213 // INST_TAG_END 00214 00215 endmodule 00216 00217 /* 00218 // MOD_TAG 00219 module xilinx_cmp8_eq (A,B,A_EQ_B); // synthesis black_box 00220 input [7 : 0] A; 00221 input [7 : 0] B; 00222 output A_EQ_B; 00223 00224 // synopsys translate_off 00225 // synthesis translate_off 00226 C_COMPARE_V1_0 #( 00227 "0", 00228 0, 00229 "0", 00230 1, 00231 1, 00232 0, 00233 0, 00234 1, 00235 0, 00236 0, 00237 0, 00238 0, 00239 0, 00240 0, 00241 0, 00242 0, 00243 0, 00244 0, 00245 0, 00246 0, 00247 0, 00248 0, 00249 0, 00250 0, 00251 1, 00252 8) 00253 inst ( 00254 .A(A), 00255 .B(B), 00256 .A_EQ_B(A_EQ_B)); 00257 // synthesis translate_on 00258 // synopsys translate_on 00259 endmodule 00260 // MOD_TAG_END 00261 * 00262 00263 // MUX 2:1 7 bits wide 00264 module mux2_7(sel, in0, in1, out); 00265 input sel; 00266 input [6:0] in0, in1; 00267 output [6:0] out; 00268 00269 // INST_TAG 00270 xilinx_mux2_7 u0 ( 00271 .MA0(in0[0]), 00272 .MA1(in0[1]), 00273 .MA2(in0[2]), 00274 .MA3(in0[3]), 00275 .MA4(in0[4]), 00276 .MA5(in0[5]), 00277 .MA6(in0[6]), 00278 00279 .MB0(in1[0]), 00280 .MB1(in1[1]), 00281 .MB2(in1[2]), 00282 .MB3(in1[3]), 00283 .MB4(in1[4]), 00284 .MB5(in1[5]), 00285 .MB6(in1[6]), 00286 00287 .S0(sel), 00288 00289 .O0(out[0]), 00290 .O1(out[1]), 00291 .O2(out[2]), 00292 .O3(out[3]), 00293 .O4(out[4]), 00294 .O5(out[5]), 00295 .O6(out[6]) ); 00296 // INST_TAG_END 00297 00298 endmodule 00299 00300 /* 00301 // MOD_TAG 00302 module xilinx_mux2_7 (MA,MB,S,O); // synthesis black_box 00303 input [6 : 0] MA; 00304 input [6 : 0] MB; 00305 input [0 : 0] S; 00306 output [6 : 0] O; 00307 00308 // synopsys translate_off 00309 // synthesis translate_off 00310 C_MUX_BUS_V1_0 #( 00311 "0000000", 00312 1, 00313 0, 00314 0, 00315 0, 00316 0, 00317 0, 00318 1, 00319 0, 00320 0, 00321 0, 00322 0, 00323 2, 00324 0, 00325 1, 00326 "0000000", 00327 0, 00328 1, 00329 7) 00330 inst ( 00331 .MA(MA), 00332 .MB(MB), 00333 .S(S), 00334 .O(O)); 00335 // synthesis translate_on 00336 // synopsys translate_on 00337 endmodule 00338 // MOD_TAG_END 00339 * 00340 00341 00342 // Mux 8:1 1 bit wide 00343 module mux8_1( sel, in, out); 00344 input [2:0] sel; 00345 input [7:0] in; 00346 output out; 00347 00348 // INST_TAG 00349 xilinx_mux8_1 u0 ( 00350 .M0(in[0]), 00351 .M1(in[1]), 00352 .M2(in[2]), 00353 .M3(in[3]), 00354 .M4(in[4]), 00355 .M5(in[5]), 00356 .M6(in[6]), 00357 .M7(in[7]), 00358 00359 .S0(sel[0]), 00360 .S1(sel[1]), 00361 .S2(sel[2]), 00362 00363 00364 .O(out)); 00365 // INST_TAG_END 00366 00367 endmodule 00368 00369 /* 00370 // MOD_TAG 00371 module xilinx_mux8_1 (M,S,O); // synthesis black_box 00372 input [7 : 0] M; 00373 input [2 : 0] S; 00374 output O; 00375 00376 // synopsys translate_off 00377 // synthesis translate_off 00378 C_MUX_BIT_V1_0 #( 00379 "0", 00380 1, 00381 0, 00382 0, 00383 0, 00384 0, 00385 1, 00386 0, 00387 0, 00388 0, 00389 0, 00390 8, 00391 3, 00392 "0", 00393 0, 00394 1) 00395 inst ( 00396 .M(M), 00397 .S(S), 00398 .O(O)); 00399 // synthesis translate_on 00400 // synopsys translate_on 00401 endmodule 00402 // MOD_TAG_END 00403 * 00404 00405 // Mux 2:1 8 bits wide 00406 module mux2_8(sel, in0, in1, out); 00407 input sel; 00408 input [7:0] in0, in1; 00409 output [7:0] out; 00410 00411 // INST_TAG 00412 xilinx_mux2_8 u0( 00413 .MA0(in0[0]), 00414 .MA1(in0[1]), 00415 .MA2(in0[2]), 00416 .MA3(in0[3]), 00417 .MA4(in0[4]), 00418 .MA5(in0[5]), 00419 .MA6(in0[6]), 00420 .MA7(in0[7]), 00421 00422 .MB0(in1[0]), 00423 .MB1(in1[1]), 00424 .MB2(in1[2]), 00425 .MB3(in1[3]), 00426 .MB4(in1[4]), 00427 .MB5(in1[5]), 00428 .MB6(in1[6]), 00429 .MB7(in1[7]), 00430 00431 .S0(sel), 00432 00433 .O0(out[0]), 00434 .O1(out[1]), 00435 .O2(out[2]), 00436 .O3(out[3]), 00437 .O4(out[4]), 00438 .O5(out[5]), 00439 .O6(out[6]), 00440 .O7(out[7]) ); 00441 // INST_TAG_END 00442 00443 endmodule 00444 00445 00446 /* 00447 // MOD_TAG 00448 module xilinx_mux2_8 (MA, MB, S, O); // synthesis black_box 00449 input [7 : 0] MA; 00450 input [7 : 0] MB; 00451 input [0 : 0] S; 00452 output [7 : 0] O; 00453 00454 // synopsys translate_off 00455 // synthesis translate_off 00456 C_MUX_BUS_V1_0 #( 00457 "00000000", 00458 1, 00459 0, 00460 0, 00461 0, 00462 0, 00463 0, 00464 1, 00465 0, 00466 0, 00467 0, 00468 0, 00469 2, 00470 0, 00471 1, 00472 "00000000", 00473 0, 00474 1, 00475 8) 00476 inst ( 00477 .MA(MA), 00478 .MB(MB), 00479 .S(S), 00480 .O(O)); 00481 // synthesis translate_on 00482 // synopsys translate_on 00483 endmodule 00484 // MOD_TAG_END 00485 * 00486 00487 // Mux 8:1 8 bits wide 00488 module mux8_8(sel, in0, in1, in2, in3, in4, in5, in6, in7, out); 00489 input [2:0] sel; 00490 input [7:0] in0, in1, in2, in3, in4, in5, in6, in7; 00491 output [7:0] out; 00492 00493 // INST_TAG 00494 xilinx_mux8_8 u0 ( 00495 .MA0(in0[0]), 00496 .MA1(in0[1]), 00497 .MA2(in0[2]), 00498 .MA3(in0[3]), 00499 .MA4(in0[4]), 00500 .MA5(in0[5]), 00501 .MA6(in0[6]), 00502 .MA7(in0[7]), 00503 00504 .MB0(in1[0]), 00505 .MB1(in1[1]), 00506 .MB2(in1[2]), 00507 .MB3(in1[3]), 00508 .MB4(in1[4]), 00509 .MB5(in1[5]), 00510 .MB6(in1[6]), 00511 .MB7(in1[7]), 00512 00513 .MC0(in2[0]), 00514 .MC1(in2[1]), 00515 .MC2(in2[2]), 00516 .MC3(in2[3]), 00517 .MC4(in2[4]), 00518 .MC5(in2[5]), 00519 .MC6(in2[6]), 00520 .MC7(in2[7]), 00521 00522 .MD0(in3[0]), 00523 .MD1(in3[1]), 00524 .MD2(in3[2]), 00525 .MD3(in3[3]), 00526 .MD4(in3[4]), 00527 .MD5(in3[5]), 00528 .MD6(in3[6]), 00529 .MD7(in3[7]), 00530 00531 .ME0(in4[0]), 00532 .ME1(in4[1]), 00533 .ME2(in4[2]), 00534 .ME3(in4[3]), 00535 .ME4(in4[4]), 00536 .ME5(in4[5]), 00537 .ME6(in4[6]), 00538 .ME7(in4[7]), 00539 00540 .MF0(in5[0]), 00541 .MF1(in5[1]), 00542 .MF2(in5[2]), 00543 .MF3(in5[3]), 00544 .MF4(in5[4]), 00545 .MF5(in5[5]), 00546 .MF6(in5[6]), 00547 .MF7(in5[7]), 00548 00549 .MG0(in6[0]), 00550 .MG1(in6[1]), 00551 .MG2(in6[2]), 00552 .MG3(in6[3]), 00553 .MG4(in6[4]), 00554 .MG5(in6[5]), 00555 .MG6(in6[6]), 00556 .MG7(in6[7]), 00557 00558 .MH0(in7[0]), 00559 .MH1(in7[1]), 00560 .MH2(in7[2]), 00561 .MH3(in7[3]), 00562 .MH4(in7[4]), 00563 .MH5(in7[5]), 00564 .MH6(in7[6]), 00565 .MH7(in7[7]), 00566 00567 .S0(sel[0]), 00568 .S1(sel[1]), 00569 .S2(sel[2]), 00570 00571 .O0(out[0]), 00572 .O1(out[1]), 00573 .O2(out[2]), 00574 .O3(out[3]), 00575 .O4(out[4]), 00576 .O5(out[5]), 00577 .O6(out[6]), 00578 .O7(out[7]) ); 00579 00580 // INST_TAG_END 00581 00582 endmodule 00583 00584 /* 00585 // MOD_TAG 00586 module xilinx_mux8_8 (MA,MB,MC,MD,ME,MF,MG,MH,S,O); // synthesis black_box 00587 input [7 : 0] MA; 00588 input [7 : 0] MB; 00589 input [7 : 0] MC; 00590 input [7 : 0] MD; 00591 input [7 : 0] ME; 00592 input [7 : 0] MF; 00593 input [7 : 0] MG; 00594 input [7 : 0] MH; 00595 input [2 : 0] S; 00596 output [7 : 0] O; 00597 00598 // synopsys translate_off 00599 // synthesis translate_off 00600 C_MUX_BUS_V1_0 #( 00601 "00000000", 00602 1, 00603 0, 00604 0, 00605 0, 00606 0, 00607 0, 00608 1, 00609 0, 00610 0, 00611 0, 00612 0, 00613 8, 00614 0, 00615 3, 00616 "00000000", 00617 0, 00618 1, 00619 8) 00620 inst ( 00621 .MA(MA), 00622 .MB(MB), 00623 .MC(MC), 00624 .MD(MD), 00625 .ME(ME), 00626 .MF(MF), 00627 .MG(MG), 00628 .MH(MH), 00629 .S(S), 00630 .O(O)); 00631 // synthesis translate_on 00632 // synopsys translate_on 00633 endmodule 00634 // MOD_TAG_END 00635 * 00636 00637 // Mux 2:1 11 bits wide 00638 module mux2_11(sel, in0, in1, out); 00639 input sel; 00640 input [10:0] in0, in1; 00641 output [10:0] out; 00642 00643 // INST_TAG 00644 xilinx_mux2_11 u0 ( 00645 .MA0(in0[0]), 00646 .MA1(in0[1]), 00647 .MA2(in0[2]), 00648 .MA3(in0[3]), 00649 .MA4(in0[4]), 00650 .MA5(in0[5]), 00651 .MA6(in0[6]), 00652 .MA7(in0[7]), 00653 .MA8(in0[8]), 00654 .MA9(in0[9]), 00655 .MA10(in0[10]), 00656 00657 .MB0(in1[0]), 00658 .MB1(in1[1]), 00659 .MB2(in1[2]), 00660 .MB3(in1[3]), 00661 .MB4(in1[4]), 00662 .MB5(in1[5]), 00663 .MB6(in1[6]), 00664 .MB7(in1[7]), 00665 .MB8(in1[8]), 00666 .MB9(in1[9]), 00667 .MB10(in1[10]), 00668 00669 .S0(sel), 00670 00671 .O0(out[0]), 00672 .O1(out[1]), 00673 .O2(out[2]), 00674 .O3(out[3]), 00675 .O4(out[4]), 00676 .O5(out[5]), 00677 .O6(out[6]), 00678 .O7(out[7]), 00679 .O8(out[8]), 00680 .O9(out[9]), 00681 .O10(out[10]) ); 00682 // INST_TAG_END 00683 00684 endmodule 00685 00686 /* 00687 // MOD_TAG 00688 module xilinx_mux2_11 (MA,MB,S,O); // synthesis black_box 00689 input [10 : 0] MA; 00690 input [10 : 0] MB; 00691 input [0 : 0] S; 00692 output [10 : 0] O; 00693 00694 // synopsys translate_off 00695 // synthesis translate_off 00696 C_MUX_BUS_V1_0 #( 00697 "00000000000", 00698 1, 00699 0, 00700 0, 00701 0, 00702 0, 00703 0, 00704 1, 00705 0, 00706 0, 00707 0, 00708 0, 00709 2, 00710 0, 00711 1, 00712 "00000000000", 00713 0, 00714 1, 00715 11) 00716 inst ( 00717 .MA(MA), 00718 .MB(MB), 00719 .S(S), 00720 .O(O)); 00721 // synthesis translate_on 00722 // synopsys translate_on 00723 endmodule 00724 // MOD_TAG_END 00725 * 00726 00727 00728 // 8bit Add/Sub with carry/borrow out 00729 module add_sub8_co(sub, opa, opb, out, co); 00730 input sub; 00731 input [7:0] opa, opb; 00732 output [7:0] out; 00733 output co; 00734 00735 wire add; 00736 assign add = ~sub; 00737 00738 // INST_TAG 00739 xilinx_add_sub8_co u0 ( 00740 .A0(opa[0]), 00741 .A1(opa[1]), 00742 .A2(opa[2]), 00743 .A3(opa[3]), 00744 .A4(opa[4]), 00745 .A5(opa[5]), 00746 .A6(opa[6]), 00747 .A7(opa[7]), 00748 00749 .B0(opb[0]), 00750 .B1(opb[1]), 00751 .B2(opb[2]), 00752 .B3(opb[3]), 00753 .B4(opb[4]), 00754 .B5(opb[5]), 00755 .B6(opb[6]), 00756 .B7(opb[7]), 00757 00758 .C_OUT(co), 00759 .ADD(add), 00760 00761 .S0(out[0]), 00762 .S1(out[1]), 00763 .S2(out[2]), 00764 .S3(out[3]), 00765 .S4(out[4]), 00766 .S5(out[5]), 00767 .S6(out[6]), 00768 .S7(out[7]) ); 00769 // INST_TAG_END 00770 00771 endmodule 00772 00773 /* 00774 // MOD_TAG 00775 module xilinx_add_sub8_co (A,B,C_OUT,ADD,S); // synthesis black_box 00776 input [7 : 0] A; 00777 input [7 : 0] B; 00778 output C_OUT; 00779 input ADD; 00780 output [7 : 0] S; 00781 00782 // synopsys translate_off 00783 // synthesis translate_off 00784 C_ADDSUB_V1_0 #( 00785 2, 00786 "0000", 00787 1, 00788 8, 00789 0, 00790 0, 00791 0, 00792 1, 00793 "0", 00794 8, 00795 1, 00796 0, 00797 1, 00798 0, 00799 0, 00800 0, 00801 0, 00802 0, 00803 0, 00804 0, 00805 0, 00806 0, 00807 1, 00808 0, 00809 0, 00810 0, 00811 0, 00812 0, 00813 1, 00814 0, 00815 0, 00816 0, 00817 7, 00818 0, 00819 8, 00820 1, 00821 "0", 00822 0, 00823 1) 00824 inst ( 00825 .A(A), 00826 .B(B), 00827 .C_OUT(C_OUT), 00828 .ADD(ADD), 00829 .S(S)); 00830 // synthesis translate_on 00831 // synopsys translate_on 00832 endmodule 00833 // MOD_TAG_END 00834 * 00835 00836 // 11 bit incrementer 00837 module inc11(in, out); 00838 input [10:0] in; 00839 output [10:0] out; 00840 00841 // INST_TAG 00842 xilinx_inc11 u0 ( 00843 .A0(in[0]), 00844 .A1(in[1]), 00845 .A2(in[2]), 00846 .A3(in[3]), 00847 .A4(in[4]), 00848 .A5(in[5]), 00849 .A6(in[6]), 00850 .A7(in[7]), 00851 .A8(in[8]), 00852 .A9(in[9]), 00853 .A10(in[10]), 00854 00855 .S0(out[0]), 00856 .S1(out[1]), 00857 .S2(out[2]), 00858 .S3(out[3]), 00859 .S4(out[4]), 00860 .S5(out[5]), 00861 .S6(out[6]), 00862 .S7(out[7]), 00863 .S8(out[8]), 00864 .S9(out[9]), 00865 .S10(out[10]) ); 00866 // INST_TAG_END 00867 00868 endmodule 00869 00870 /* 00871 // MOD_TAG 00872 module xilinx_inc11 (A,S); // synthesis black_box 00873 input [10 : 0] A; 00874 output [10 : 0] S; 00875 00876 // synopsys translate_off 00877 // synthesis translate_off 00878 C_ADDSUB_V1_0 #( 00879 0, 00880 "0000", 00881 1, 00882 11, 00883 0, 00884 0, 00885 1, 00886 1, 00887 "0001", 00888 11, 00889 1, 00890 0, 00891 0, 00892 0, 00893 0, 00894 0, 00895 0, 00896 0, 00897 0, 00898 0, 00899 0, 00900 0, 00901 0, 00902 0, 00903 0, 00904 0, 00905 0, 00906 0, 00907 1, 00908 0, 00909 0, 00910 0, 00911 10, 00912 0, 00913 11, 00914 1, 00915 "0", 00916 0, 00917 1) 00918 inst ( 00919 .A(A), 00920 .S(S)); 00921 // synthesis translate_on 00922 // synopsys translate_on 00923 endmodule 00924 // MOD_TAG_END 00925 * 00926 00927 // 8 bit incrementer 00928 module inc8(in, out); 00929 input [7:0] in; 00930 output [7:0] out; 00931 00932 // INST_TAG 00933 xilinx_inc8 u0 ( 00934 .A0(in[0]), 00935 .A1(in[1]), 00936 .A2(in[2]), 00937 .A3(in[3]), 00938 .A4(in[4]), 00939 .A5(in[5]), 00940 .A6(in[6]), 00941 .A7(in[7]), 00942 00943 .S0(out[0]), 00944 .S1(out[1]), 00945 .S2(out[2]), 00946 .S3(out[3]), 00947 .S4(out[4]), 00948 .S5(out[5]), 00949 .S6(out[6]), 00950 .S7(out[7]) ); 00951 // INST_TAG_END 00952 00953 endmodule 00954 00955 /* 00956 // MOD_TAG 00957 module xilinx_inc8 (A,S); // synthesis black_box 00958 input [7 : 0] A; 00959 output [7 : 0] S; 00960 00961 // synopsys translate_off 00962 // synthesis translate_off 00963 C_ADDSUB_V1_0 #( 00964 0, 00965 "0000", 00966 1, 00967 8, 00968 0, 00969 0, 00970 1, 00971 1, 00972 "0001", 00973 8, 00974 1, 00975 0, 00976 0, 00977 0, 00978 0, 00979 0, 00980 0, 00981 0, 00982 0, 00983 0, 00984 0, 00985 0, 00986 0, 00987 0, 00988 0, 00989 0, 00990 0, 00991 0, 00992 1, 00993 0, 00994 0, 00995 0, 00996 7, 00997 0, 00998 8, 00999 1, 01000 "0", 01001 0, 01002 1) 01003 inst ( 01004 .A(A), 01005 .S(S)); 01006 // synthesis translate_on 01007 // synopsys translate_on 01008 endmodule 01009 // MOD_TAG_END 01010 * 01011 01012 01013 // A Basic Synchrounous FIFO (4 entries deep) 01014 module sfifo4x11(clk, push, din, pop, dout); 01015 input clk; 01016 input push; 01017 input [10:0] din; 01018 input pop; 01019 output [10:0] dout; 01020 01021 reg [10:0] stack1, stack2, stack3, stack4; 01022 01023 assign dout = stack1; 01024 01025 always @(posedge clk) 01026 begin 01027 if(push) // PUSH stack 01028 begin 01029 stack4 <= #1 stack3; 01030 stack3 <= #1 stack2; 01031 stack2 <= #1 stack1; 01032 stack1 <= #1 din; 01033 end 01034 if(pop) // POP stack 01035 begin 01036 stack1 <= #1 stack2; 01037 stack2 <= #1 stack3; 01038 stack3 <= #1 stack4; 01039 end 01040 end 01041 01042 endmodule 01043 01044 01045 // Synchrounous SRAM 01046 // 128 bytes by 8 bits 01047 // 1 read port, 1 write port 01048 // FOR XILINX VERTEX SERIES 01049 module ssram_128x8(clk, rd_addr, rd_data, we, wr_addr, wr_data); 01050 input clk; 01051 input [6:0] rd_addr; 01052 output [7:0] rd_data; 01053 input we; 01054 input [6:0] wr_addr; 01055 input [7:0] wr_data; 01056 01057 wire [7:0] tmp; 01058 01059 01060 // Alternatively RAMs can be instantiated directly 01061 RAMB4_S8_S8 u0( 01062 .DOA( rd_data ), 01063 .ADDRA( {2'b0, rd_addr} ), 01064 .DIA( 8'h00 ), 01065 .ENA( 1'b1 ), 01066 .CLKA( clk ), 01067 .WEA( 1'b0 ), 01068 .RSTA( 1'b0 ), 01069 .DOB( tmp ), 01070 .ADDRB( {2'b0, wr_addr} ), 01071 .DIB( wr_data ), 01072 .ENB( 1'b1 ), 01073 .CLKB( clk ), 01074 .WEB( we ), 01075 .RSTB( 1'b0 ) ); 01076 01077 01078 endmodule 01079 01080 01081 01082 // This block is the global Set/Rest for Xilinx VIrtex Serries 01083 // Connect it up as described in Xilinx documentation 01084 // Leave it out for Non Xilinx implementations 01085 module glbl(rst); 01086 input rst; 01087 01088 wire GSR; 01089 01090 assign GSR = rst; 01091 01092 endmodule 01093 01094