Processes | |
PROCESS_4 | ( clk ) |
Signals | |
ones | integer RANGE 0 TO 6 := 0 |
bits | integer RANGE 0 TO 7 := 0 |
mem | std_logic |
counterOne | integer := 0 |
PROCESS_4 | ( | clk ) |
ones integer RANGE 0 TO 6 := 0 [Signal] |
bits integer RANGE 0 TO 7 := 0 [Signal] |
mem std_logic [Signal] |
counterOne integer := 0 [Signal] |