00001 ///////////////////////////////////////////////////////////////////// 00002 //// //// 00003 //// Mini-RISC-1 //// 00004 //// Mini-Risc Core Top Levcel //// 00005 //// //// 00006 //// //// 00007 //// Author: Rudolf Usselmann //// 00008 //// rudi@asics.ws //// 00009 //// //// 00010 //// //// 00011 //// D/L from: http://www.opencores.org/cores/minirisc/ //// 00012 //// //// 00013 ///////////////////////////////////////////////////////////////////// 00014 //// //// 00015 //// Copyright (C) 2000-2002 Rudolf Usselmann //// 00016 //// www.asics.ws //// 00017 //// rudi@asics.ws //// 00018 //// //// 00019 //// This source file may be used and distributed without //// 00020 //// restriction provided that this copyright statement is not //// 00021 //// removed from the file and that any derivative work contains //// 00022 //// the original copyright notice and the associated disclaimer.//// 00023 //// //// 00024 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// 00025 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// 00026 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// 00027 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// 00028 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 00029 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// 00030 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// 00031 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// 00032 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// 00033 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 00034 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// 00035 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// 00036 //// POSSIBILITY OF SUCH DAMAGE. //// 00037 //// //// 00038 ///////////////////////////////////////////////////////////////////// 00039 00040 // CVS Log 00041 // 00042 // $Id: risc_core_top.v,v 1.3 2002/10/01 12:44:24 rudi Exp $ 00043 // 00044 // $Date: 2002/10/01 12:44:24 $ 00045 // $Revision: 1.3 $ 00046 // $Author: rudi $ 00047 // $Locker: $ 00048 // $State: Exp $ 00049 // 00050 // Change History: 00051 // $Log: risc_core_top.v,v $ 00052 // Revision 1.3 2002/10/01 12:44:24 rudi 00053 // Tweaked code a bit - trying to get it run faster ... 00054 // 00055 // Revision 1.2 2002/09/27 15:35:40 rudi 00056 // Minor update to newer devices ... 00057 // 00058 // 00059 // 00060 // 00061 // 00062 // 00063 // 00064 // 00065 // 00066 // 00067 // 00068 00069 `timescale 1ns / 10ps 00070 00071 module mrisc_top( 00072 clk, rst_in, 00073 porta, portb, portc, 00074 tcki, 00075 wdt_en ); // synthesis syn_useioff=1 syn_hier="flatten,remove" 00076 00077 // Basic Core I/O. 00078 input clk; 00079 input rst_in; 00080 00081 // I/O Ports 00082 inout [7:0] porta; 00083 inout [7:0] portb; 00084 inout [7:0] portc; 00085 00086 input tcki; 00087 input wdt_en; 00088 00089 //////////////////////////////////////////////////////////////////////// 00090 // 00091 // Local Wires 00092 // 00093 00094 wire [10:0] inst_addr; 00095 wire [11:0] inst_data; 00096 00097 wire [7:0] portain; 00098 wire [7:0] portbin; 00099 wire [7:0] portcin; 00100 00101 wire [7:0] portaout; 00102 wire [7:0] portbout; 00103 wire [7:0] portcout; 00104 00105 wire [7:0] trisa; 00106 wire [7:0] trisb; 00107 wire [7:0] trisc; 00108 00109 //////////////////////////////////////////////////////////////////////// 00110 // 00111 // IO Buffers 00112 // 00113 00114 assign porta[0] = trisa[0] ? 1'bz : portaout[0]; 00115 assign porta[1] = trisa[1] ? 1'bz : portaout[1]; 00116 assign porta[2] = trisa[2] ? 1'bz : portaout[2]; 00117 assign porta[3] = trisa[3] ? 1'bz : portaout[3]; 00118 assign porta[4] = trisa[4] ? 1'bz : portaout[4]; 00119 assign porta[5] = trisa[5] ? 1'bz : portaout[5]; 00120 assign porta[6] = trisa[6] ? 1'bz : portaout[6]; 00121 assign porta[7] = trisa[7] ? 1'bz : portaout[7]; 00122 00123 assign portb[0] = trisb[0] ? 1'bz : portbout[0]; 00124 assign portb[1] = trisb[1] ? 1'bz : portbout[1]; 00125 assign portb[2] = trisb[2] ? 1'bz : portbout[2]; 00126 assign portb[3] = trisb[3] ? 1'bz : portbout[3]; 00127 assign portb[4] = trisb[4] ? 1'bz : portbout[4]; 00128 assign portb[5] = trisb[5] ? 1'bz : portbout[5]; 00129 assign portb[6] = trisb[6] ? 1'bz : portbout[6]; 00130 assign portb[7] = trisb[7] ? 1'bz : portbout[7]; 00131 00132 assign portc[0] = trisc[0] ? 1'bz : portcout[0]; 00133 assign portc[1] = trisc[1] ? 1'bz : portcout[1]; 00134 assign portc[2] = trisc[2] ? 1'bz : portcout[2]; 00135 assign portc[3] = trisc[3] ? 1'bz : portcout[3]; 00136 assign portc[4] = trisc[4] ? 1'bz : portcout[4]; 00137 assign portc[5] = trisc[5] ? 1'bz : portcout[5]; 00138 assign portc[6] = trisc[6] ? 1'bz : portcout[6]; 00139 assign portc[7] = trisc[7] ? 1'bz : portcout[7]; 00140 00141 assign portain = porta; 00142 assign portbin = portb; 00143 assign portcin = portc; 00144 00145 //////////////////////////////////////////////////////////////////////// 00146 // 00147 // Mini Risc Core 00148 // 00149 00150 mrisc u0( 00151 clk, 00152 rst_in, 00153 00154 inst_addr, 00155 inst_data, 00156 00157 portain, 00158 portbin, 00159 portcin, 00160 00161 portaout, 00162 portbout, 00163 portcout, 00164 00165 trisa, 00166 trisb, 00167 trisc, 00168 00169 tcki, 00170 wdt_en ); 00171 00172 00173 //////////////////////////////////////////////////////////////////////// 00174 // 00175 // Program memory 00176 // 00177 00178 generic_spram #(11,12) imem( 00179 .clk( clk ), 00180 .rst( rst_in ), 00181 .ce( 1'b1 ), 00182 .we( 1'b0 ), 00183 .oe( 1'b1 ), 00184 .addr( inst_addr ), 00185 .di( 12'h0 ), 00186 .do( inst_data ) 00187 ); 00188 00189 endmodule