Ports | |
clk | |
rd_addr | |
rd_data | |
we | |
wr_addr | |
wr_data | |
Includes | |
C_ADDSUB_V1_0 | |
C_MUX_BUS_V1_0 | |
C_COMPARE_V1_0 | |
C_MUX_BIT_V1_0 | |
C_MEM_DP_BLOCK_V1_0 | |
C_REG_FD_V1_0 | |
Inputs | |
clk | |
rd_addr | [ 6 : 0 ] |
we | |
wr_addr | [ 6 : 0 ] |
wr_data | [ 7 : 0 ] |
Outputs | |
rd_data | [ 7 : 0 ] |
Components | |
u0 | RAMB4_S8_S8 |
Definition at line 1049 of file primitives_xilinx.v.
clk [Ports] |
Definition at line 1049 of file primitives_xilinx.v.
rd_addr [Ports] |
Definition at line 1049 of file primitives_xilinx.v.
rd_data [Ports] |
Definition at line 1049 of file primitives_xilinx.v.
we [Ports] |
Definition at line 1049 of file primitives_xilinx.v.
wr_addr [Ports] |
Definition at line 1049 of file primitives_xilinx.v.
wr_data [Ports] |
Definition at line 1049 of file primitives_xilinx.v.
clk [Inputs] |
Definition at line 1050 of file primitives_xilinx.v.
rd_addr [ 6 : 0 ] [Inputs] |
Definition at line 1051 of file primitives_xilinx.v.
rd_data [ 7 : 0 ] [Outputs] |
Definition at line 1052 of file primitives_xilinx.v.
we [Inputs] |
Definition at line 1053 of file primitives_xilinx.v.
wr_addr [ 6 : 0 ] [Inputs] |
Definition at line 1054 of file primitives_xilinx.v.
wr_data [ 7 : 0 ] [Inputs] |
Definition at line 1055 of file primitives_xilinx.v.
u0 RAMB4_S8_S8 [Components] |
Definition at line 1061 of file primitives_xilinx.v.
C_ADDSUB_V1_0 include [Includes] |
Definition at line 73 of file primitives_xilinx.v.
C_MUX_BUS_V1_0 include [Includes] |
Definition at line 74 of file primitives_xilinx.v.
C_COMPARE_V1_0 include [Includes] |
Definition at line 75 of file primitives_xilinx.v.
C_MUX_BIT_V1_0 include [Includes] |
Definition at line 76 of file primitives_xilinx.v.
C_MEM_DP_BLOCK_V1_0 include [Includes] |
Definition at line 77 of file primitives_xilinx.v.
C_REG_FD_V1_0 include [Includes] |
Definition at line 78 of file primitives_xilinx.v.