convergence.mixed Architecture Reference

Inheritance diagram for convergence.mixed:

convergence

List of all members.


Processes

PROCESS_0  ( clk )

Signals

irq_mask  std_logic_vector ( 3 downto 0 )
irq_unmasked  std_logic_vector ( 3 downto 0 )
irq_status  std_logic_vector ( 3 downto 0 )
reset_cnt  integer RANGE 0 TO 7
irq_read  std_logic
wr  std_logic
rd  std_logic
w_err  std_logic

Components

irq_w_error 
irq_bl  Entity <irq_bl>


Member Function Documentation

[Process]
PROCESS_0 ( clk )


Member Data Documentation

irq_w_error [Component]

irq_bl [Component]

irq_mask std_logic_vector ( 3 downto 0 ) [Signal]

irq_unmasked std_logic_vector ( 3 downto 0 ) [Signal]

irq_status std_logic_vector ( 3 downto 0 ) [Signal]

reset_cnt integer RANGE 0 TO 7 [Signal]

irq_read std_logic [Signal]

wr std_logic [Signal]

rd std_logic [Signal]

w_err std_logic [Signal]

irq0 PORT [Port Map]

irq1 PORT [Port Map]

irq2 PORT [Port Map]

irq3 PORT [Port Map]

irq4 PORT [Port Map]


The documentation for this class was generated from the following file:

Generated on Sat Apr 19 14:13:49 2008 by  doxygen 1.5.4-20071103